參數(shù)資料
型號: S1C88816D
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164
封裝: DIE-164
文件頁數(shù): 38/173頁
文件大小: 1411K
代理商: S1C88816D
124
EPSON
S1C88816 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter)
Example)
Terminal setting:
PAD5=1, PAD7=PAD6=PAD4=0
(AD5 terminal is used)
Selection of input channel:
CHS1=0, CHS0=0
(AD4 is selected)
In a setting like this, the A/D conversion
result will be invalid because the contents of
the settings are not matched.
Setting of input clock (PSAD)
Turning clock output ON (PRAD)
Setting of analog input terminals
(PAD)
Writing to CHS register
=selection of analog input channel
Writing to ADRUN register
=starting A/D conversion
Fig. 5.15.4.1 Flowchart for starting A/D conversion
An A/D conversion is completed when the conver-
sion result is loaded into the ADDR register. At that
point, the A/D converter generates an interrupt
(explained in the next section).
Figure 5.15.4.2 shows the timing chart of A/D
conversion.
5.15.5 Interrupt function
The A/D converter can generate an interrupt when
an A/D conversion has completed.
Figure 5.15.5.1 shows the configuration of the A/D
converter interrupt circuit.
The A/D converter sets the interrupt factor flag
FAD to "1" when it stores the conversion.
At this time, if the interrupt enable register EAD is
"1" and the interrupt priority register PADC (2 bits)
is set to a higher level than the setting of the
interrupt flags (I0 and I1), an interrupt is generated
to the CPU.
By setting the EAD register to "0", the interrupt to
the CPU can also be disabled. However, the
interrupt factor flag is set to "1" when an A/D
conversion has completed regardless of the inter-
rupt enable register and interrupt priority register
settings.
The interrupt factor flag set in "1" is reset to "0" by
writing "1".
Refer to Section 5.16, "Interrupt and Standby
Status", for details of the interrupt control registers
and operations subsequent to interrupt generation.
The exception processing vector address for the
A/D conversion completion interrupt has been set
in 000024H.
Writing to ADRUN register
Input sampling
Successive conversion
ADDR register
Interrupt request
tAD
Sampling time
8tCLK
tAD:
tCLK:
0 to 1tCLK
Input clock cycle
Conversion result
A/D conversion time
21tCLK+tAD
Fig. 5.15.4.2 Timing chart of A/D conversion
Data
bus
Interrupt
request
Address
A/D conversion
completion
Interrupt factor flag
FAD
Address
Interrupt enable
register EAD
Interrupt priority
level judgment
circuit
Address
Interrupt priority register
PADC0, PADC1
Fig. 5.15.5.1 Configuration of A/D converter interrupt circuit
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