參數(shù)資料
型號(hào)： S1C88816D
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164
封裝： DIE-164
文件頁數(shù)： 30/173頁
文件大?。?/td> 1411K
代理商： S1C88816D
S1C88816 TECHNICAL MANUAL
EPSON
117
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Melody Generator)
PMDY0, PMDY1: 00FF28HD4, D5
Sets the priority level of the melody interrupt.
Table 5.13.5.3 shows the interrupt priority level that
can be set by the PMDY register.
Table 5.13.5.3 Interrupt priority level settings
PMDY1
PMDY0
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
EMDY: 00FF2AHD6
Enables or disables the melody interrupt generation
to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading:
Valid
The EMDY register is the interrupt enable register
corresponding to the melody completion interrupt
factor. When this register is set to "1", the interrupt
is enabled, and when it is set to "0", the interrupt is
disabled.
At initial reset, this register is set to "0" (interrupt is
disabled).
FMDY: 00FF2CHD6
Indicates the generation of a melody completion
interrupt factor.
When "1" is read:
Int. factor present
When "0" is read:
Int. factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
FMDY is the interrupt factor flag corresponding to
the melody interrupt and is set to "1" when play is
completed.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding interrupt
priority register is set to a higher level than the
setting of the interrupt flags (I0 and I1), an interrupt
is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt
generation condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower level
than the level indicated by the interrupt priority
registers, or execute the RETE instruction) and to
reset the interrupt factor flag. The interrupt factor
flag is reset to "0" by writing "1".
At initial reset, this flag is set to "0".
5.13.6 Programming notes
(1) Tempo cannot be changed in the middle of a
melody.
(2) The note RAM and scale RAM cannot be
accessed from the CPU while a melody is
playing (MBUSY = "1").
A melody play continues until the note being
played has finished even if MTC is set to "0".
Make sure that a melody play has actually
finished using MBUSY or an interrupt before
the melody RAM can be accessed.
(3) Do not set a tie to the first note of a melody to
prevent improper operation.
(4) Set 00H or an available scale data to the scale
RAM address corresponding to a rest. Writing
FFH may cause improper operation.
(5) When the SLP instruction is executed during a
melody play, an unstable signal will be output
from the MOUT and MOUT terminals at the
time of returning from SLEEP status. Therefore,
set MTC to "0" and make sure that MBUSY goes
"0" before setting the CPU into SLEEP status.
(6) Direct driving a piezoelectric buzzer is
recommended for melody output for lower
current consumption.
When driving an external bipolar transistor
with the melody signal, select "heavy load
protection mode during melody output" by
mask option. Note that the LCD driver current
will be increased about 20 A.
When direct driving a piezoelectric buzzer,
select "normal mode" by mask option to reduce
current consumption.
(7) The S1C88816 melody generator uses a RAM for
storing melody data. Therefore, the user must
arrange for permission to use the melodies to be
stored if they are copyrighted.
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