- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98069 > S1C88816D 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C88816D |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164 |
| 封裝： | DIE-164 |
| 文件頁(yè)數(shù)： | 129/173頁(yè) |
| 文件大?。?/td> | 1411K |
| 代理商： | S1C88816D |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)當(dāng)前第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)
S1C88816 TECHNICAL MANUAL
EPSON
51
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.7.5 Transmit-receive control
Below is a description of the registers which handle
transmit-receive control. With respect to transmit-
receive control procedures and operations, please
refer to the following sections in which these are
discussed on a mode by mode basis.
s Shift register and received data buffer
Exclusive shift registers for transmitting and
receiving are installed in this serial interface.
Consequently, duplex communication simultane-
ous transmit and receive is possible when the
asynchronous system is selected.
Data being transmitted are written to TRXD0–
TRXD7 and converted to serial through the shift
register and is output from the SOUT terminal.
In the reception section, a received data buffer is
installed separate from the shift register.
Data being received are input to the SIN terminal
and is converted to parallel through the shift
register and written to the received data buffer.
Since the received data buffer can be read even
during serial input operation, the continuous data
is received efficiently.
However, since buffer functions are not used in
clock synchronous mode, be sure to read out data
before the next data reception begins.
s Transmit enable register and transmit
control bit
For transmitting control, use the transmit enable
register TXEN and transmit control bit TXTRG.
The transmit enable register TXEN is used to set the
transmitting enable/disable status. When "1" is
written to this register to set the transmitting enable
status, clock input to the shift register is enabled
and the system is ready to transmit data. In the
clock synchronous mode, synchronous clock input/
output from the SCLK terminal is also enabled.
The transmit control bit TXTRG is used as the
trigger to start transmitting data.
Data to be transmitted is written to the transmit
data shift register, and when transmitting prepara-
tions a recomplete, "1" is written to TXTRG where-
upon data transmitting begins.
When interrupt has been enabled, an interrupt is
generated when the transmission is completed. If
there is subsequent data to be transmitted it can be
sent using this interrupt.
In addition, TXTRG can be read as the status. When
set to "1", it indicates transmitting operation, and
"0" indicates transmitting stop.
For details on timing, see the timing chart which
gives the timing for each mode.
When not transmitting, set TXEN to "0" to disable
transmitting status.
s Receive enable register, receive control bit
For receiving control, use the receive enable register
RXEN and receive control bit RXTRG.
Receive enable register RXEN is used to set receiv-
ing enable/disable status. When "1" is written into
this register to set the receiving enable status, clock
input to the shift register is enabled and the system
is ready to receive data. In the clock synchronous
mode, synchronous clock input/output from the
SCLK terminal is also enabled.
With the above setting, receiving begins and serial
data input from the SIN terminal goes to the shift
register.
The operation of the receive control bit RXTRG is
slightly different depending on whether a clock
synchronous system or an asynchronous system is
being used.
In the clock synchronous system, the receive
control bit TXTRG is used as the trigger to start
receiving data.
When received data has been read and the prepara-
tion for next data receiving is completed, write "1"
into RXTRG to start receiving. (When "1" is written
to RXTRG in slave mode, SRDY switches to "0".)
In an asynchronous system, RXTRG is used to
prepare for next data receiving. After reading the
received data from the received data buffer, write
"1" into RXTRG to signify that the received data
buffer is empty. If "1" is not written into RXTRG,
the overrun error flag OER will be set to "1" when
the next receiving operation is completed. (An
overrun error will be generated when receiving is
completed between reading the received data and
the writing of "1" to RXTRG.)
In addition, RXTRG can be read as the status. In
either clock synchronous mode or asynchronous
mode, when RXTRG is set to "1", it indicates
receiving operation and when set to "0", it indicates
that receiving has stopped.
For details on timing, see the timing chart which
gives the timing for each mode.
When you do not receive, set RXEN to "0" to disable
receiving status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C88832F0A0100 | MICROCONTROLLER, PQFP128 |
| S1C88848D0A0100 | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192 |
| S1C8F360F | 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176 |
| S1D13305F00B | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
| S1D13305F00A | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C88848 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C8F360D411000 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| S1C8F360D511000 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| S1C8F360F413100 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| S1C8F360F513200 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。