參數(shù)資料
型號(hào): S1C88816D
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164
封裝: DIE-164
文件頁(yè)數(shù): 140/173頁(yè)
文件大?。?/td> 1411K
代理商: S1C88816D
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)當(dāng)前第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)
S1C88816 TECHNICAL MANUAL
EPSON
61
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
Data
bus
Interrupt
request
Address
Error generation
Interrupt factor
flag
FSERR
Address
Interrupt enable
register ESERR
Address
Receive completion
Interrupt factor
flag
FSREC
Address
Interrupt enable
register ESREC
Address
Transmit completion
Interrupt factor
flag
FSTRA
Address
Interrupt enable
register ESTRA
Interrupt priority
level judgement
circuit
Address
Interrupt priority
register PSIF0, PSIF1
s Receiving complete interrupt
This interrupt factor is generated at the point where
receiving has been completed and the receive data
incorporated into the shift register has been trans-
ferred into the received data buffer and it sets the
interrupt factor flag FSREC to "1". When set in this
manner, if the corresponding interrupt enable
register ESREC is set to "1" and the corresponding
interrupt priority registers PSIF0 and PSIF1 are set to
a higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
When "0" has been written into the interrupt enable
register ESREC and interrupt has been disabled, an
interrupt is not generated to the CPU. Even in this
case, the interrupt factor flag FSREC is set to "1".
The interrupt factor flag FSREC is reset to "0" by
writing "1".
The generation of this interrupt factor permits the
received data to be read.
Also, the interrupt factor flag is set to "1" when a
parity error or framing error is generated.
The exception processing vector address for this
interrupt factor is set at 000012H.
s Error interrupt
This interrupt factor is generated at the point where
a parity error, framing error or overrun error is
detected during receiving and it sets the interrupt
factor flag FSERR to "1". When set in this manner, if
the corresponding interrupt enable register ESERR
is set to "1" and the corresponding interrupt priority
registers PSIF0 and PSIF1 are set to a higher level
than the setting of interrupt flags (I0 and I1), an
interrupt will be generated to the CPU.
When "0" has been written in the interrupt enable
register ESERR and interrupt has been disabled, an
interrupt is not generated to the CPU. Even in this
case, the interrupt factor flag FSERR is set to "1".
The interrupt factor flag FSERR is reset to "0" by
writing "1".
Since all three types of errors result in the same
interrupt factor, you should identify the error that
has been generated by the error flags PER (parity
error), OER (overrun error) and FER (framing
error).
The exception processing vector address for this
interrupt factor is set at 000010H.
Fig. 5.7.8.1 Configuration of serial interface interrupt circuit
相關(guān)PDF資料
PDF描述
S1C88832F0A0100 MICROCONTROLLER, PQFP128
S1C88848D0A0100 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
S1C8F360F 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176
S1D13305F00B 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60
S1D13305F00A 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S1C88848 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer
S1C8F360D411000 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT
S1C8F360D511000 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT
S1C8F360F413100 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT
S1C8F360F513200 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT