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參數(shù)資料
| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 91/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
34
Freescale Semiconductor
enable, RTIE, to allow masking of the real-time interrupt. It can be disabled by writing 0:0:0 to RTIS2:RTIS1:RTIS0 so the timer
is disabled and no interrupts will be generated. See Section 5.9.8 for more detail on this register and control bits.
5.8
Temperature Sensor and Restart System
The MPXY8300 Series of devices have two temperature sensing mechanisms. The first is an accurate sensor which is accessible
through the ADC10 channel 1 whenever the ADC10 is enabled. The second is a less accurate, very low power sensor which
generates a wake-up from either stop1 or stop2 when the temperature drops below its threshold of detection if the TRE bit is set
in the SOPT2. This is the temperature restart wake-up which is used as follows:
1.
The temperature restart wake-up is enabled by software following detection of an over temperature condition using the
temperature sensor connected to the ADC10.
2.
The temperature triggered wake-up is enabled by setting the TRE bit in SOPT2.
3.
User software instructs the MCU to enter either stop1 or stop2 mode to halt execution during the over temperature
condition.
4.
When the temperature falls below the temperature restart threshold, TRESET, a wake-up is generated to wake the MCU.
Exit from stop1 or stop2 will reset the device.
5.9
Reset, Interrupt, and System Control Registers and Control Bits
This section describes the registers associated with general system control of the MCU.
Refer to the direct-page register summary in Section 4, for the absolute address assignments for all registers. This section refers
to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into
the appropriate absolute addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these
bits are provided here, the related functions are discussed in greater detail in Section 3.
5.9.1
Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and
one write-only bit. These bits are used to configure the IRQ function, report status, and acknowledge IRQ events.
7
6
5
4
3
2
1
0
R
0
IRQEDG
IRQPE
IRQF
0
IRQIE
IRQMOD
W
IRQACK
Reset
0
= Unimplemented or Reserved
Figure 5-2 Interrupt Request Status and Control Register (IRQSC)
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