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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 136/162頁 |
| 文件大小： | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
75
TPMMODH:TPMMODL = 0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS = 0,
this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter needs a valid
match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting.
Figure 9-11 shows the output compare value in the TPM channel registers (multiplied by 2), which determines the pulse width
(duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a
compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in
TPMMODH:TPMMODL, then counts down until it reaches zero. This sets the period equal to two times TPMMODH:TPMMODL.
Figure 9-11 CPWM Period and Pulse Width (ELSnA = 0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined
up at the same system clock edge. This type of PWM is also required for some types of motor drives.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit
updates and to avoid unexpected PWM pulse widths. Writes to any of the registers, TPMMODH, TPMMODL, TPMCnVH, and
TPMCnVL, actually write to buffer registers. Values are transferred to the corresponding timer channel registers only after both
8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-
counting at the end of the terminal count in the modulus register). This TPMCNT overflow requirement only applies to PWM
channels, not output compares.
Optionally, when TPMCNTH:TPMCNTL = TPMMODH:TPMMODL, the TPM can generate a TOF interrupt at the end of this
count. The user can choose to reload any number of the PWM buffers, and they will all update simultaneously at the start of a
new period.
Writing to TPMSC cancels any values written to TPMMODH and/or TPMMODL and resets the coherency mechanism for the
modulo registers. Writing to TPMCnSC cancels any values written to the channel value registers and resets the coherency
mechanism for TPMCnVH:TPMCnVL.
9.5
TPM Interrupts
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel
interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is
set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM modes, the
interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. See Section 5 for
absolute interrupt vector addresses, priority, and local interrupt mask control bits.
For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel
input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an
associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set,
a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to
perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine.
9.5.1
Clearing Timer Interrupt Flags
TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1) followed by a write of 0
to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the
second step to avoid the possibility of missing the new event.
9.5.2
Timer Overflow Interrupt Description
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the 16-bit
timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the
PERIOD
PULSE WIDTH
COUNT =
COUNT = 0
OUTPUT
COMPARE
(COUNT UP)
OUTPUT
COMPARE
(COUNT DOWN)
COUNT =
TPMMODH:TPMM
TPM1C
TPMMODH:TPMM
2 x
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相關(guān)代理商/技術(shù)參數(shù) |
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| PPYY12C0.75 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket Material:PVC (Polyvinyl Chloride), External Diameter:9.9mm, |
| PPYY12C0.75 100M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 100M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Met 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Metric):100m, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket , RoHS Compliant: Yes |
| PPYY12C0.75 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 50M |
| PPYY12C1.50 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, PER M |
| PPYY12C1.50 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, 50M |
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