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| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 81/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
25
4.8.2
FLASH Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5 through 2 are not used
and always read 0. This register may be read at any time, but writes have no meaning or effect. To change the value in this
register, erase and reprogram the NVOPT location in FLASH memory as usual and then issue a new MCU reset.
Table 4-5 FCDIV Register Field Descriptions
Field
Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regard-
less of the data written.
0
FCDIV has not been written since reset; erase and program operations disabled for FLASH
1
FCDIV has been written since reset; erase and program operations enabled for FLASH
6
PRDIV8
Prescale (Divide) FLASH Clock by 8
0
Clock input to the FLASH clock divider is the bus rate clock
1
Clock input to the FLASH clock divider is the bus rate clock divided by 8
5:0
DIV[5:0]
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Pro-
gram/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5
μs to
6.7
μs. The automated programming logic uses an integer number of these pulses to complete an erase or pro-
gram operation.
if PRDIV8 = 0 — fFCLK = fBus ÷ ([DIV5:DIV0] + 1)
if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × ([DIV5:DIV0] + 1))
Table 4-6 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
Table 4-6 FLASH Clock Divider Settings
fBus
PRDIV8
(Binary)
DIV5:DIV0
(Decimal)
fFCLK
Program/Erase Timing Pulse
(5
μs Min, 6.7 μs Max)
20 MHz
1
12
192.3 kHz
5.2
μs
10 MHz
0
49
200 kHz
5
μs
8 MHz
0
39
200 kHz
5
μs
4 MHz
0
19
200 kHz
5
μs
2 MHz
0
9
200 kHz
5
μs
1 MHz
0
4
200 kHz
5
μs
200 kHz
0
200 kHz
5
μs
150 kHz
0
150 kHz
6.7
μs
7
6
5
4
3
2
1
0
R
KEYEN
FNORED
0
SEC01
SEC00
W
Reset:
This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-6 FLASH Options Register (FOPT)
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