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參數(shù)資料
| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 43/162頁 |
| 文件大小： | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
137
Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the
last location in the FIFO. By reading DBGFH then DBGFL periodically, external host software can develop a profile of program
execution. After eight reads from the FIFO, the ninth read will return the information that was stored as a result of the first read.
To use the profiling feature, read the FIFO eight times without using the data to prime the sequence and then begin using the
data to get a delayed picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL
(while the FIFO is not armed) is the address of the most-recently fetched opcode.
15.4.3.7
Debug Control Register (DBGC)
This register can be read or written at any time.
7
6
5
4
3
2
1
0
R
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
W
Reset
0
Figure 15-7 Debug Control Register (DBGC)
Table 15-4 DBGC Register Field Descriptions
Field
Description
7
DBGEN
Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
0
DBG disabled
1
DBG enabled
6
ARM
Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is
used to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be
manually stopped by writing 0 to ARM or to DBGEN.
0
Debugger not armed
1
Debugger armed
5
TAG
Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If
BRKEN = 0, this bit has no meaning or effect.
0
CPU breaks requested as force type requests
1
CPU breaks requested as tag type requests
4
BRKEN
Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can
cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace,
CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements.
For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the
timing of CPU break requests.
0
CPU break requests not enabled
1
Triggers cause a break request to the CPU
3
RWA
R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write
access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.
0
Comparator A can only match on a write cycle
1
Comparator A can only match on a read cycle
2
RWAEN
Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.
0
R/W is not used in comparison A
1
R/W is used in comparison A
1
RWB
R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write
access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.
0
Comparator B can match only on a write cycle
1
Comparator B can match only on a read cycle
0
RWBEN
Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.
0
R/W is not used in comparison B
1
R/W is used in comparison B
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