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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 135/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
74
Freescale Semiconductor
9.4.2.2
Output Compare Mode
With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and
frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set,
clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of
a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control
register (TPMCnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
9.4.2.3
Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can be used when other
channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is
determined by the setting in the modulus register (TPMMODH:TPMMODL). The duty cycle is determined by the setting in the
timer channel value register (TPMCnVH:TPMCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA
control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As Figure 9-10 shows, the output compare value in the TPM channel registers determines the pulse width (duty cycle) of the
PWM signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA = 0, the counter
overflow forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the counter overflow
forces the PWM signal low and the output compare forces the PWM signal high.
Figure 9-10 PWM Period and Pulse Width (ELSnA = 0)
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel value register
(TPMCnVH:TPMCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the
modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit
updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMCnVH or TPMCnVL, write to buffer registers.
In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit
register have been written and the value in the TPMCNTH:TPMCNTL counter is 0x0000. (The new duty cycle does not take effect
until the next full period.)
9.4.3
Center-Aligned PWM Mode
This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in
TPMCnVH:TPMCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in
TPMMODH:TPMMODL. TPMMODH:TPMMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this
range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPMCnVH:TPMCnVL)
period = 2 x (TPMMODH:TPMMODL);
for TPMMODH:TPMMODL = 0x0001–0x7FFF
If the channel value register TPMCnVH:TPMCnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If
TPMCnVH:TPMCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be
100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is
0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is not necessary). This is not a significant limitation because
the resulting period is much longer than required for normal applications.
PERIOD
PULSE
WIDTH
OVERFLOW
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
TPMCH
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