參數(shù)資料
型號: PPXY8300A6T1
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: Pressure Sensor
英文描述: DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝: SOIC-20
文件頁數(shù): 76/162頁
文件大?。?/td> 4316K
代理商: PPXY8300A6T1
MPXY8300 Series
Sensors
20
Freescale Semiconductor
4.6.1
Features
Features of the FLASH memory include:
User Program FLASH Size — 8192 bytes (16 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
4.6.2
Program and Erase Times
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must be written to set the
internal clock for the FLASH module to a frequency (fFCLK) between 150 kHz and 200 kHz (see Section 4.8.1). This register can
be written only once, so normally this write is performed during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period
of the resulting clock (1/fFCLK) is used by the command processor to time program and erase pulses. An integer number of these
timing pulses are used by the command processor to complete a program or erase command.
Table 4-4 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (fFCLK). The
time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number of cycles of FCLK and as an absolute time for
the case where tFCLK = 5 μs. Program and erase times shown include overhead for the command state machine and enabling
and disabling of program and erase voltages.
4.6.3
Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared
before beginning command execution. The command execution steps are:
1.
Write a data value to an address in the FLASH array. The address and data information from this write is latched into
the FLASH interface. This write is a required first step in any command sequence. For erase and blank check
commands, the value of the data is not important. For page erase commands, the address may be any address in the
512-byte page of FLASH to be erased. For mass erase and blank check commands, the address can be any address
in the FLASH memory. Whole pages of 512 bytes are the smallest block of FLASH that may be erased.
NOTE
Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits
to a byte which is already programmed is not allowed without first erasing the page in which the byte resides or
mass erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the
FLASH.
2.
Write the command code for the desired command to FCMD. The five valid commands are blank check (0x05), byte
program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into
the command buffer.
3.
Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data
information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to the memory array and
before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR
access error flag which must be cleared before starting a new command.
Table 4-4 Program and Erase Times
Parameter
Cycles of FCLK
Time if FCLK = 200 kHz
Byte program
9
45
μs
Byte program (burst)
4
20
μs(1)
NOTES:
1. Excluding start/end overhead
Page erase
4000
20 ms
Mass erase
20,000
100 ms
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