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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 112/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
53
8.3
Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers,
and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any
memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access
I/O and control registers or nonvolatile program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing mode to specify the
source operand and a second addressing mode to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ,
and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to
specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing
mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
8.3.1
Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does
not need to access memory to get any operands.
Table 8-1 CCR Register Field Descriptions
Field
Description
7
V
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0
No overflow
1
Overflow
4
H
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 dur-
ing an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0
No carry between bits 3 and 4
1
Carry between bits 3 and 4
3
I
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automat-
ically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service routine
is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an interven-
ing interrupt, provided I was set.
0
Interrupts enabled
1
Interrupts disabled
2
N
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipu-
lation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0
Non-negative result
1
Negative result
1
Z
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation pro-
duces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded
or stored value was all 0s.
0
Non-zero result
1Zero result
0
C
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
0
No carry out of bit 7
1
Carry out of bit 7
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| PPYY12C0.75 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket Material:PVC (Polyvinyl Chloride), External Diameter:9.9mm, |
| PPYY12C0.75 100M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 100M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Met 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Metric):100m, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket , RoHS Compliant: Yes |
| PPYY12C0.75 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 50M |
| PPYY12C1.50 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, PER M |
| PPYY12C1.50 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, 50M |
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