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| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 22/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
118
Freescale Semiconductor
13.6.7
PLL Trim Register - RFXTRIM1
The RFXTRIM1 register contain trim and control bits for the RFX as described in Figure 13-15. This register is accessed by
writing to the RFX register address $08 using the SPI.
13.7
Datagram Transmission Times
In order to comply with FCC requirements in the US market the periodically transmitted datagram must be less than 1 second in
length and be separated by an off time that is at least 10 seconds or at least 30 times longer than the transmission time, whichever
is longer. The user software must adhere to this ruling for products intended for the US market.
13.8
Charge Pump
The RFX contains a charge pump which generates a voltage up to the maximum level of VCAPMAX. A block diagram of the charge
pump is shown in Figure 13-16. The charge pump is enabled by the CPUMP bit in the RFCR2 register. When CPUMP is set an
internal RC charge pump oscillator (CPO) is powered up to provide the switching clock for the charge pump. An internally
switched, charging capacitor charges up an external capacitor connected to the VCAP pin.
The CPO output frequency, fCPO, is used by a time-out timer that sets a maximum time, tCHG, that is set by the CPT bits.
After the tCHG expires the charge pump will be turned off and the CPUMP bit cleared. However, if the voltage on the VCAP pin
reaches the maximum threshold of the voltage sense, VCHGMAX, then the charge pump will be turned off and the CPUMP bit
cleared before the tCHG time has elapsed. The MCU can check the status of the charging cycle by poling the CPUMP bit. The
MCU can also terminate the charge cycle early by clearing the CPUMP bit. During the charge cycle both the AVDD and VCAP
control bits should be clear so there can be no reverse current back to AVDD if the voltage on the VCAP pin is charged above the
AVDD pin.
$07 [1]
MOD
RF Modulation Method — The MOD control bit selects the method of modulating the RF. The MOD control bit
is cleared by a RFX reset.
0
Configured for ASK
1
Configured for FSK
$07 [0]
CKREF
Reference Clock Enable — The CKREF control bit controls the output of a reference clock to the MCU via the
Dx signal. It is recommended that the CKREF bit be cleared before initiating an RF transmission to reduce spu-
rious noise. The CKREF control bit is cleared by a RFX reset.
0
Reference clock signal disabled
1
Reference clock connected to the MCU
$08
Bit 7
6
5
4
3
2
1
Bit 0
R
0
DISCHARGE
0
1
W
RESET:
0
1
Figure 13-15 RFX Trim Register (RFXTRIM1)
Table 13-10 RFXTRIM Register Field Descriptions
Field
Description
$08 [7-6]
Reserved
Reserved
$08 [5]
DISCHARGE
Charge Pump Capacitor Discharge— This bit controls an internal discharge path from VCAP to VSS of approx-
imately 17 mV/msec from 68
μF capacitor. The DISCHARGE control bit is cleared by a RFX reset.
0
Discharge path off
1
Discharge path on
$08 [4-0]
Reserved
Reserved
Table 13-9 PLL Control Registers B Field Descriptions (Continued)
Field
Description
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