參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 158/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
Freescale Semiconductor
95
12.5.4
Wake-Up Code
The wake-up code is a series of Manchester bits that can have 8 or 16 Manchester bits as defined by the LFWU8 bit. The
wake-up code A with 8 bits (LFWU8 is one) is stored in LFCA0 register. The wake-up code A with 16 bits (LFWU8 is zero)
is stored in LFCA1 (most significant byte) and LFCA0 (least significant byte) registers. The wake-up code B with 8 bits
(LFWU8 is one) is stored in LFCB0 register. The wake-up code B with 16 bits (LFWU8 is zero) is stored in LFCB1 (most
significant byte) and LFCB0 (least significant byte) registers.
The wake-up code is received most significant bit first.
If the received wake-up code matches with the wake-up code A, then the LFAF bit is set. The LFAF bit is cleared when a ‘1’
is written in the LFDFAK bit.
If the received wake-up code matches with the wake-up code B, then the LFBF bit is set. The LFBF is cleared when a ‘1’ is
written in the LFDFAK bit.
Therefore, the MCU can determine which wake-up code was received by reading the LFAF and LFBF flag bits. If neither of
the wake-up codes were matched then the LFR detector and MFO are turned off and the LFR decoder is reset for tRST. If a
matching code was received the LFR detector and MFO will remain powered up to allow reception of any subsequent data
bytes being transmitted.
12.5.5
Data Bytes
Following a successful match in wake-up code, additional data may be decoded as 8-bit bytes. The data bytes are received
most significant bit first. After the last bit in each 8-bit byte is decoded, the data will be loaded into the LFDATA register, the
data ready flag LFDF will be set and the LFR interrupt will be generated (if the LFIE bit is set).
The LFR interrupt will be deactivated when the LFDF bit is cleared. The LFDF is cleared when a ‘1’ is written in the LFDFAK
bit.
The MCU can then check the LFDF flag for a data byte being received and read the 8-bit data in the LFDATA register.
Subsequent 8-bit bytes of data will continue to generate new interrupts and the most current data will overwrite the contents
of the LFDATA register. Therefore the LFDATA register contents will be lost if the MCU fails to read the data before the LFR
decodes the next byte.
The LFR detector and MFO will remain powered up as long as there is Manchester data being received. When the LFR
decoder receives a Manchester data that is not valid (Manchester code violation), it treats it as the end of LF data frame.
LFR decoder sets MDDO bit, generates LFR interrupt (if the LFIE bit is set), turns off LFR detector and MFO (if the MFO
clock is not also being used by the ACI or PCI at that time), and LFR decoder is reset for tRST.
The LFR interrupt will be cleared when the MDDO bit is cleared. The MDDO is cleared when a ‘1’ is written to the LFDFAK
bit or a ‘0’ is written to the LFEN bit.
12.5.6
LF Reset Time
When the reset time period, tRST, is initiated the LFOFF bit will be set. When the tRST time expires the LFOFF bit will be
cleared. The reset time period is a multiple of the sample period that is selected by the LFRST bit.
12.6
Register Descriptions
12.6.1
LF Wake-Up Code A — Byte 0 (LFCA0) Register
7
6
5
4
3
2
1
0
R
LFA[7:0]
W
Reset
0
Figure 12-12 LF Wake-Up Code A — Byte 0 (LFCA0) Register
Table 12-2 LFCA0 Field Descriptions
Field
Description
7–0
LFA[7:0]
Wake-Up Code A — 8 least significant bits.
The LFCA0 register contains the least significant byte (bits 0 until 7) of one of the wake-up codes (code A)
required in a LF Manchester datagram. Write to these bits is only effective when LFEN=0.
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相關代理商/技術參數(shù)
參數(shù)描述
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