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參數(shù)資料
| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 33/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
128
Freescale Semiconductor
Figure 15-2 BDC Host-to-Target Serial Bit Timing
Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU.
The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release
the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time.
The host should sample the bit level about 10 cycles after it started the bit time.
Figure 15-3 BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target
MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it
drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the
bit level about 10 cycles after starting the bit time.
EARLIEST START
TARGET SENSES BIT LEVEL
10 CYCLES
YNCHRONIZATION
UNCERTAINTY
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED START
OF BIT TIME
OF NEXT BIT
HOST SAMPLES BKGD PIN
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
BKGD PIN
R-C RISE
10 CYCLES
EARLIEST START
OF NEXT BIT
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