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參數(shù)資料
| 型號： | PowerPC 740 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 608K |
| 代理商： | POWERPC 740 |
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12/8/99
Version 1.02
Page7
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
System unit
- Executes CR logical instructions and miscellaneous system instructions.
- Special register transfer instructions.
Cache structure
- 32K, 32-byte line, 8-way set associative instruction cache.
- 32K, 32-byte line, 8-way set associative data cache.
- Single-cycle cache access.
- Pseudo-LRU replacement.
- Copy-back or write-through data cache (on a page per page basis).
- Supports all PowerPC memory coherency modes.
- Non-blocking instruction and data cache (one outstanding miss under hits).
- No snooping of instruction cache.
Memory management unit
- 128 entry, 2-way set associative instruction TLB.
- 128 entry, 2-way set associative data TLB.
- Hardware reload for TLB's.
- 4 instruction BAT's and 4 data BATs.
- Virtual memory support for up to 4 exabytes (2
52
) virtual memory.
- Real memory support for up to 4 gigabytes (2
32
) of physical memory.
Level 2 (L2) cache interface (Not available on the 740)
- Internal L2 cache controller and 4K-entry tags; external data SRAMs.
- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support.
- Copy-back or write-through data cache (on a page basis, or for all L2).
- 64-byte (256K/512K) and 128-byte (l-Mbyte) sectored line size.
- Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst
SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs with optional parity checking.
- Supports Core-to-L2 frequency divisors of
÷
1,
÷
1.5,
÷
2,
÷
2.5, and
÷
3. The 750 supports the L2 fre-
quency range specified in Section “L2 Clock AC Specifications,” on page 18. For higher L2 frequen-
cies, please contact ppcsupp@us.ibm.com.
Bus interface
- Compatible with 60x processor interface.
- 32-bit address bus with optional parity checking.
- 64-bit data bus (can be operated in 32-bit data bus mode) with optional parity checking.
- Bus-to-core frequency multipliers from 2x to 10x. See the Table , “PLL Configuration,” on page 36.
Integrated power management
- Low-power 2.0/3.3V design.
- Three static power saving modes: doze, nap, and sleep.
- Automatic dynamic power reduction when internal functional units are idle.
Integrated Thermal Management Assist Unit
- On-chip thermal sensor and control logic.
- Thermal Management Interrupts for software regulation of junction temperature.
Testability
- JTAG interface.
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