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參數(shù)資料
| 型號： | PowerPC 740 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 37/48頁 |
| 文件大?。?/td> | 608K |
| 代理商： | POWERPC 740 |
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12/8/99
Version 1.02
Page37
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PLL Power Supply Filtering
The AV
DD
and L2AVdd are power signals provided on the 750 to provide power to the clock generation phase-
locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power
supplied to the AV
DD
input signal should be filtered using a circuit similar to the one shown in Figure 18. The
circuit should be placed as close as possible to the AV
DD
pin to ensure it filters out as much noise as possible.
For dd3.2, AVdd is filtered on the module from Vdd for the 750 only and can be connected or not, at the
designer’s convenience. The 740 requires AVdd to be supplied as usual.
Decoupling Recommendations
Due to the dynamic power management of the 750, which features large address and data buses, as well as
high operating frequencies, the 750 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the 750 system, and the 750 itself requires a clean, tightly regulated source of power.
Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with
a low ESR (effective series resistance) rating at each V
DD
and OV
DD
pin (and L2OV
DD
for the 360 CBGA) of the
750. It is also recommended that these decoupling capacitors receive their power from separate V
DD
, OV
DD
and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should range in value from 220pF to 10
μ
F to provide both high- and low-frequency filtering,
and should be placed as close as possible to their associated V
DD
or OV
DD
pins. Suggested values for the V
DD
pins – 220pF (ceramic), 0.01
μ
F (ceramic), and 0.1
μ
f (ceramic). Suggested values for the OV
DD
pins – 0.01
μ
F
(ceramic), 0.1
μ
f (ceramic), and 10
μ
F (tantalum). Only SMT (surface-mount technology) capacitors should be
used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feed-
ing the V
DD
and OV
DD
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors – 100
μ
F (AVX TPS tantalum) or 330
μ
F (AVX TPS tantalum).
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to V
DD
. Unused active high inputs should be connected to GND.
All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD
, OV
DD
, and GND, pins of the 750.
Figure 18. PLL Power Supply Filter Circuit
VDD
AV
DD
(or L2AV
DD
)
10
10
μ
F
0.1
μ
F
GND
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