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參數(shù)資料
| 型號： | PowerPC 740 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 608K |
| 代理商： | POWERPC 740 |
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12/8/99
Version 1.02
Page33
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Note:
1. For dd3.x on the 750 only, AVdd is no longer connected to the BGA pin. AVdd is filtered on the module
from Vdd. The 740 dd3.2 does require AVdd.
2. BVSEL and L2VSEL Function
If BVSEL or L2VSEL is connected to GND with a series resistor, the resistor value must be 10
or less.
3. These are test signals for factory use only and must be pulled up to OVdd for normal operation. During
normal operation, L2_TSTCLK can be connected to GND if required.
4. These pins are reserved for potential future use as additional L2 address pins.
5. OVdd inputs supply power to the I/O drivers, and Vdd inputs supply power to the processor core.
6. Internally tied to L2OV
DD
in the 750 360 CBGA package. This is NOT a supply pin.
PowerPC 750 Package
Package Type
Ceramic Ball Grid Array (CBGA)
Package outline
25 x 25mm
Interconnects
360 (19 x 19 ball array - 1)
Pitch
1.27mm (50mil)
Minimum module height
2.65mm
Maximum module height
3.20mm
Ball diameter
0.89mm (35mil)
TSIZ[0:2]
A9, B9, C9
High
Output
TT[0:4]
C10, D11, B12, C12, F11
High
I/O
WT
C3
Low
Output
VDD
5
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
—
—
VOLTDET
6
K13
High
Output
Unconnected
L2OVdd = 3.3 V nominal
Connected to HRESET
OVdd = 2.5 V nominal
Connected to GND
OVdd = 1.8 V nominal
Pinout Listing for the PowerPC 750 360 CBGA package (cont.)
Signal Name
Pin Number
Active
I/O
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