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參數(shù)資料
| 型號： | PowerPC 740 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 21/48頁 |
| 文件大小： | 608K |
| 代理商： | POWERPC 740 |
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12/8/99
Version 1.02
Page21
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Bus Output AC Specifications
L2 Bus Output Interface AC Timing Specifications
1
See Table “Recommended Operating Conditions,” on page 9 for operating conditions, C
L
= 20pF
3
Num
Characteristic
L2CR[14:15] is equivalent to:
Unit
Notes
00
2
01
10
11
Min
Max
Min
Max
Min
Max
Min
Max
26
L2SYNC_IN to output valid,
Fmax
7
up through 375 MHz.
—
3.2
—
3.7
—
Rsv
5
—
Rsv
5
ns
26
L2SYNC_IN to output valid, Fmax
= 400 MHz.
—
3.0
—
3.5
—
Rsv
5
—
Rsv
5
ns
26
L2SYNC_IN to output valid, Fmax
= 433 and 450 MHz.
—
2.6
—
3.1
—
Rsv
5
—
Rsv
5
ns
26
L2SYNC_IN to output valid, Fmax
= 466 and 500 MHz.
—
2.4
—
2.9
—
Rsv
5
—
Rsv
5
ns
27
L2SYNC_IN to output hold
0.5
—
1.0
—
Rsv
5
—
Rsv
5
—
ns
4,6
28
L2SYNC_IN to high impedance
—
3.5
—
4.0
—
Rsv
5
—
Rsv
5
ns
6
Note:
1. All outputs are measured from the Vm of the rising edge of L2SYNC_IN to the Vm of the signal in question. The output timings are measured at the pins
(see Figure 8).
2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-through and pipelined reg-reg synchronous burst SRAMs,
L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 01 is recommended.
3. All maximum timing specifications assume CL = 20pF.
4. This measurement assumes CL= 5pF.
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
7. Specifications are shown as a Function of Maximum Core Frequency (Fmax). They refer to the effective Fmax of the part after derating for application
conditions. For example, a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet or exceed the specifica-
tions shown for Fmax = 400 MHz.
Figure 8. L2 Bus Output Timing Diagrams
27
VM
L2SYNC_IN
26
ALL OUTPUTS
VM
28
L2DATA BUS
VM
VM
Vm = 1.4 V for L2OVdd = 3.3 V., else Vm = L2OVdd/2
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