參數(shù)資料
型號(hào)： PowerPC 740
廠商： IBM Microeletronics
英文描述： 32-Bit Embedded Microprocessor(32位精簡(jiǎn)指令集嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位精簡(jiǎn)指令集嵌入式微處理器）
文件頁(yè)數(shù)： 20/48頁(yè)
文件大小： 608K
代理商： POWERPC 740
Page 20
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Bus Input AC Specifications
Some specifications are shown in the following table as a Function of Maximum Core Frequency (Fmax).
These specifications refer to the effective Fmax of the part after derating for application conditions. For exam-
ple, a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet or
exceed the specifications shown for Fmax = 400 MHz.
L2 Bus Input Interface AC Timing Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
Min
Max
Unit
Notes
29,30
L2SYNC_IN rise and fall time
—
1.0
ns
2,3
24
Data and parity input setup to L2SYNC_IN, Fmax up
through 375 MHz.
1.5
—
ns
1
24
Data and parity input setup to L2SYNC_IN, Fmax = 400
MHz.
1.4
—
ns
1
24
Data and parity input setup to L2SYNC_IN, Fmax = 433 and
450 MHz.
1.1
—
ns
1
24
Data and parity input setup to L2SYNC_IN, Fmax = 466 and
500 MHz.
1.0
—
ns
1
25
L2SYNC_IN to data and parity input hold
0.5
—
ns
1
Note:
1. All input specifications are measured from the Vm of the signal in question to the Vm of the rising edge of the input L2SYNC_IN. Input timings are
measured at the pins (see Figure 7).
2. Rise and fall times for the L2SYNC_IN input are measured from 0.5 to 1.5V.
3. Guaranteed by design and characterization, and not tested.
Figure 7. L2 Bus Input Timing Diagrams
VM
L2SYNC_IN
25
24
ALL INPUTS
29
30
VM
VM
Vm = 1.4 V for L2OVdd = 3.3 V., else Vm = L2OVdd/2
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