參數(shù)資料
型號(hào)： PowerPC 740
廠商： IBM Microeletronics
英文描述： 32-Bit Embedded Microprocessor(32位精簡(jiǎn)指令集嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位精簡(jiǎn)指令集嵌入式微處理器）
文件頁(yè)數(shù)： 39/48頁(yè)
文件大小： 608K
代理商： POWERPC 740
12/8/99
Version 1.02
Page39
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pull-up Resistor Requirements
The 750 requires high-resistive (weak: 10K
) pull-up resistors on several control signals of the bus interface
to maintain the control signals in the negated state after they have been actively negated and released by the
750 or other bus masters. These signals are: TS, ABB, DBB, TBST, GBL, and ARTRY.
In addition, the 750 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7K
- 1K
) if it is used by the system. This signal is: CKSTP_OUT.
If address or data parity is not used by the system, it should be disabled using HID0. This also disables the
parity input receivers. In most systems, the unused (and disabled) parity pins can be left unconnected; how-
ever, in some systems, these parity pins must be pulled up to OVdd by a weak (or stronger) pull-up.
No pull-up resistors are normally required for the L2 interface, the 60x bus address and AP lines, or the 60x
bus data and DP lines. The data bus input receivers are normally turned off when no read operation is in
progress and do not require pull-up resistors on the data bus.
HRESET and GBL must be actively driven.
Resistor Pull-up / Pull-down Requirements
Required or Recommended Actions
Signals
Strong pull-up required
CKSTP_OUT
Weak pull-up required
TLBISYNC, LSSD_MODE, L1_TSTCLK, L2TSTCLK, TS, ABB, DBB, ARTRY,
GBL, TBST
Weak pull-up or pull-down required
TCK
Weak pull-up recommended
SRESET, SMI, INT, MCP, CKSTP_IN
Weak pull-up recommended if pin not used
AP[0:3], DP[0:3]
Errata Summary
#
Problem
Description
Impact
Solution(s)
Applies to
Version 3.2
1
L2 cache invalidate may
fail with DPM enabled.
If DPM is enabled during
a global invalidate of the
L2 cache, the global
invalidate may not invali-
date all the L2’s tags.
Possible system failure
after L2 initialization and
start-up.
Turn DPM off during a
L2 tag invalidate.
Yes
3
dcbz that hits in L1
cache may not retry
snoop.
If a dcbz hits in the L1
cache, a snoop received
at the same time to that
address may not be ser-
viced or get retried.
Stale data from system
memory may be read by
the other bus master,
and the line may
become valid in multiple
caches.
Limit use of dcbz to
data that is protected
through software syn-
chronization.
Yes
5
Segment register
updates may corrupt
data translation.
mtsr<in> followed by an
instruction causing a
page data address trans-
lation can cause conten-
tion for the segment
registers.
Possible access to incor-
rect real address loca-
tions or false translation
and data access excep-
tions.
Insert isync, sc, or rfi
between andy mtsr<in>
and instructions that
cause a page data
address translation.
Yes
8
(
Advisory
)
Stfd of uninitialized FPR
can hang part.
A stfd will hang the part if
its source FPR has pow-
ered up in a certain
state.
Any system using a stfd. Initialize all FPRs at
POR.
Yes
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