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參數(shù)資料
| 型號： | PowerPC 740 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 4/48頁 |
| 文件大?。?/td> | 608K |
| 代理商： | POWERPC 740 |
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Page 4
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Preface
The PowerPC 740 and PowerPC 750 are members of the PowerPC family of reduced instruction set com-
puter (RISC) microprocessors. The PPC740L and PPC750L microprocessors are the PID-8p implementa-
tions of the PowerPC 740 and PowerPC 750 in IBM CMOS 7S 0.20
μ
m copper technology. They are referred
to in the body of this document as “740“ and “750.”
Information in this document does not apply to implementations of the PowerPC 740 and PowerPC 750 in
other technologies, such as the PID-8t.
The information in this document is also specific to revision level dd3.2 of the (PID-8p) PPC740L and
PPC750L, and does not apply to previous revisions.
This document is generally written in terms of the 750. Unless otherwise noted, information that applies to the
750 also applies to the 740. Exceptions are detailed. The 740 die is identical to the 750 die, but the 740 pack-
age and pinout are different, in that the 740 does not pin out the L2 interface.
The 740 uses the same die as the 750, but the 740 does not pin out the L2 cache interface.
New Features for dd3.x
Selectable I/O voltages on 60X bus and L2 bus. See Table , “Recommended Operating Conditions,” on
page 9. Older revs must leave these pins “no connect” or “tied high” for 3.3v I/Os. Ac timings are the
same for all I/O voltages modes unless otherwise noted.
60X bus to core frequency now also supports the 10x ratio. See Table , “PLL Configuration,” on page 36.
Extra output hold on the 60x bus by L2_TSTCLK pin tied low is no longer available. The L2_TSTCLK pin
must now be tied to OV
DD
for normal operation. See Table , “60X Bus Output AC Timing Specifications for
the 750
1
,” on page 16.
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