參數(shù)資料
型號: PowerNP NPe405H
廠商: IBM Microeletronics
英文描述: 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述: 32位嵌入式處理器(32位嵌入式處理器)
文件頁數(shù): 8/64頁
文件大?。?/td> 1050K
代理商: POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
8
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC
processor and local memory. This interface is compliant with version 2.2 of the PCI Specification.
Features include:
Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use
is optional and can be disabled for systems which employ an external arbiter.
PLB 3.0 Compliant
PLB bus frequency up to 133MHz
64-bit PLB Master
32-bit PLB Slave
PCI bus frequency up to 66MHz
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
32-bit PCI Address/Data Bus
Power Management:
- PCI Bus Power Management v1.1 compliant
Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
Buffering between PLB and PCI:
- PCI Target 64-byte write post buffer
- PCI Target 96-byte read prefetch buffer
- PLB Slave 8-byte write post buffer
- PLB Slave 64-byte read prefetch buffer
Error tracking/status
Supports PCI Target side configuration
Supports processor access to all PCI address spaces:
- Single-byte PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes
- Single-byte PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
Supports PCI target access to all PLB address spaces
Supports PowerPC processor boot from PCI memory
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