參數(shù)資料
型號(hào)： PowerNP NPe405H
廠商： IBM Microeletronics
英文描述： 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述： 32位嵌入式處理器（32位嵌入式處理器）
文件頁(yè)數(shù)： 59/64頁(yè)
文件大小： 1050K
代理商： POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
59
PHY0Col[PHY0Rx1Er]l
PHY0CrS[PHY0CrS0DV]
PHY0RxClk
PHY0RxD0:3
[PHY0Rx0:1D0:1]
[PHY0Rx0:3D]
PHY0RxDV
[PHY0CRS1DV]
PHY0RxErr[PHY0Rx0Er]
PHY0TxClk[PHY0RefClk]
[PHY1RxD0:3]
[PHY1Rx2:3D0:1]
[PHY1Col]
[PHY1Rx3Er]
[PHY1CrS]
[PHY1CrS2DV]
[PHY1RxClk]
[PHY1RxDV]
[PHY1CrS3DV]
[PHY1RxErr]
[PHY1Rx2Er]
[PHY1TxClk]
HDLCEX Interface
HDLCEXRxClk
HDLCEXRxDataA:B
HDLCEXRxFS
HDLCEXTxClk
HDLCEXTxDataA:B
HDLCEXTxFS
HDLCEXTxEnA
[CGPIO24][UART1_RTS]
HDLCEXTxEnB
[CGPIO25][UART1_DTR]
HDLCMP Interface
HDLCMPTxClk0:3
[HDLCMPTxClk4:7]
HDLCMPTxData0:3
async[0.1]
async[0.1]
n/a
1.5
[0.8]
[0.8]
async[1.4]
async[1.5]
n/a
1.4
[1.3]
[0.2]
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
1
1, async
n/a
n/a
n/a
n/a
PHYRX
1
1.3[0.7]
1.3[1.3]
n/a
n/a
n/a
n/a
PHYRX
1
1.3[0.7]
n/a
1.4[1.5]
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
PHYRX
1
1, async
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
23.8
24.2
n/a
n/a
24.2
n/a
1.5
0.8
n/a
n/a
0.8
n/a
n/a
n/a
n/a
7.6
n/a
n/a
n/a
n/a
n/a
3.3
n/a
n/a
n/a
n/a
n/a
12
n/a
n/a
n/a
n/a
n/a
8
n/a
n/a
n/a
8.5
3.5
12
8
n/a
n/a
8.9/
3.8
12
8
n/a
n/a
12
n/a
n/a
8
I/O Specifications—266MHz
(Part 2 of 5)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3.
SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
6.
PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns
for 33MHz.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
相關(guān)PDF資料
PDF描述
PowerNP NPe405L 32-Bit Embedded Processor(32位嵌入式處理器)
PowerNP NPe405 32-Bit Embedded Processor(32位嵌入式處理器（應(yīng)用于網(wǎng)絡(luò)方面，提供高性價(jià)比）)
PowerPC 401GF 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
PowerPC 403GA 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
PowerPC 403GB 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
POWERPAC-B 制造商:IAR Systems 功能描述:PowerPac
POWERPAC-S 制造商:IAR Systems 功能描述:PowerPac
POWERPAT PLUS 制造商:Fluke Electronics 功能描述:SOFTWARE PAT
POWERPATPLUS 制造商:Fluke Electronics 功能描述:Fluke Powerpat Plus
POWERPLUG15W 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:AC/DC POWER SUPPLY
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*