參數(shù)資料
型號(hào): PowerNP NPe405H
廠商: IBM Microeletronics
英文描述: 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述: 32位嵌入式處理器(32位嵌入式處理器)
文件頁數(shù): 42/64頁
文件大?。?/td> 1050K
代理商: POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
42
PerR/W
Used by the NPe405H when not in external master mode,
as an output by either the peripheral controller or DMA
controller depending upon the type of transfer involved.
High indicates a read from memory, low indicates a write to
memory.
Otherwise it used by the external master as an input to
indicate the direction of transfer.
I/O
5V tolerant
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to transfer
data.
I
5V tolerant
3.3V LVTTL
1
PerBLast
Used by the NPe405H when not in external master mode,
otherwise used by external master. Indicates the last
transfer of a memory access.
I/O
5V tolerant
3.3V LVTTL
1, 4
PerClk
Peripheral Clock to be used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
PerErr
Used as an input to record external master and slave
peripheral errors.
I
5V tolerant
3.3V LVTTL
1, 5
[DMAReq0:3]
Used by slave peripherals to indicate they are prepared to
transfer data.
I
5V tolerant
3.3V LVTTL
1, 5
[DMAAck0:3]
Used by the NPe405H to indicate that data transfers have
occurred.
O
5V tolerant
3.3V LVTTL
[EOT0:3][TC0:3]
End Of Transfer[Terminal Count].
I/O
5V tolerant
3.3V LVTTL
1, 5
Signal Functional Description
(Part 6 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
Signal Name
Description
I/O
Type
Notes
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