參數(shù)資料
型號(hào)： PowerNP NPe405H
廠商： IBM Microeletronics
英文描述： 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述： 32位嵌入式處理器（32位嵌入式處理器）
文件頁(yè)數(shù)： 41/64頁(yè)
文件大小： 1050K
代理商： POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
41
BA1:0
Bank Address supporting up to 4 internal banks
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lanes 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7.
I/O
3.3V LVTTL
4
BankSel0:3
Select up to four external SDRAM banks.
O
3.3V LVTTL
WE
Write Enable.
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases,
glueless SDRAM attachment without requiring this signal
to be repowered by a PLL or zero-delay buffer.
O
3.3V LVTTL
External Slave Peripheral Interface
PerData0:31
Peripheral data bus used by NPe405H when not in
external master mode, otherwise used by external master.
Note:
PerData00 is the most significant bit (msb) on this
bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr4:31
Peripheral Address bus used by NPe405H when not in
external master mode, otherwise used by external master.
I/O
5V tolerant
3.3V LVTTL
1
PerPar0:3
Peripheral byte parity signals.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:3
As outputs, these pins can act as byte-enables which are
valid for an entire cycle or as write-byte-enables which are
valid for each byte on each data transfer, allowing partial
word transactions. As outputs, pins are used by either
peripheral controller or DMA controller depending upon the
type of transfer involved. Used as inputs when external bus
master owns the external interface.
I/O
5V tolerant
3.3V LVTTL
1, 2
PerWE
Peripheral Write Enable. Low when any of the four
PerWBE signals are low.
I/O
5V tolerant
3.3V LVTTL
[PerCS0:7]
Peripheral Chip Selects
O
5V tolerant
3.3V LVTTL
2
PerOE
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
NPe405H is the bus master, it enables the selected
SDRAMs to drive the bus.
O
5V tolerant
3.3V LVTTL
2
Signal Functional Description
(Part 5 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
Signal Name
Description
I/O
Type
Notes
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