參數(shù)資料
型號： PowerNP NPe405H
廠商： IBM Microeletronics
英文描述： 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述： 32位嵌入式處理器（32位嵌入式處理器）
文件頁數(shù)： 57/64頁
文件大小： 1050K
代理商： POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
57
External Slave Peripheral Interface
DMAReq0:3[SGPIO9:12]
DMAAck0:3[SGPIO13:16]
EOT0:3[TC0:3]
[SGPIO24:27]
PerAddr4:31
PerBLast
PerCS0:7
PerData0:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
PerClk
PerErr
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
4.8
n/a
0.0
n/a
7.0
7.5
1.1
1.1
n/a
12
n/a
8
PerClk
PerClk
4.3
-0.1
8.5
1.2
12
8
PerClk
n/a
n/a
n/a
4.8
n/a
3.1
n/a
7.5
n/a
n/a
4.0
n/a
n/a
n/a
1.0
n/a
0.0
n/a
-0.5
n/a
n/a
-0.6
8.5
7.4
7.2
9.3
7.6
8.3
7.5
n/a
7.5
0.5
n/a
0.9
1.4
1.3
1.0
1.4
0.9
1.4
n/a
1.3
-0.9
n/a
17
12
12
17
12
17
12
n/a
12
17
n/a
11
8
8
11
8
11
8
n/a
8
11
n/a
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
5
n/a
n/a
5
n/a
n/a
4
5
n/a
n/a
1
n/a
n/a
1
1
8
7
0
0
12
12
n/a
19
12
n/a
n/a
8
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
8
8
n/a
n/a
n/a
0
0
n/a
n/a
n/a
12
8
n/a
n/a
I/O Specifications—200MHz
(Part 5 of 5)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3.
SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
6.
PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns
for 33MHz.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
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