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參數(shù)資料
| 型號： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 1/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
Features
TM
NPe405L Embedded Processor Data Sheet
1
IBM PowerPC
core operating up to 266 MHz
TM
405 32-bit RISC processor
PC-100 Synchronous DRAM (SDRAM)
interface operating up to 133 MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
External Peripheral Bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, or 16-bit SRAM and
external peripherals
- Up to 4 banks
DMA support for external peripherals, internal
UARTs and memory
- Scatter-gather chaining supported
- Four channels
2 Ethernet 10/100Mbps (full-duplex) units with
a choice of MII, RMII, or SMII interfaces.
HDLC interface with 32 channels through 2
ports
Programmable Interrupt Controllers supports
interrupts from a variety of sources
- Seven external and 29 internal
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor
core
- Programmable critical interrupt priority
ordering
- Programmable critical interrupt vector for
faster vector processing
Programmable Timers
Two serial ports (16550 compatible UART)
One IIC (I
2
C) interface
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
Description
Designed specifically to address embedded
applications, the NPe405L provides a high-
performance, low-power solution that interfaces to a
wide range of peripherals by incorporating on-chip
power management features and intrinsically lower
power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, Ethernet
interfaces, HDLC interface, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS 6SF 0.25
(0.18
μ
m L
eff
)
μ
m
Package: 324-ball (23mm) enhanced plastic ball
grid array (E-PBGA)
Power (estimated): Typical 1.1W, Maximum .W
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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