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參數(shù)資料
| 型號： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 45/48頁 |
| 文件大小： | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
45
[UART0_DSR]
[UART0_DTR]
[UART0_RI]
[UART0_RTS]
UART0_Rx
UART0_Tx
[UART1_CTS]
[UART1_DCD]GPIO28
[HDLCEXTxEnA]
[UART1_DSR]
[UART1_DTR]
[UART1_RI]GPIO29
[HDLCEXTxEnB]
[UART1_RTS]
UART1_Rx
UART1_Tx
UARTSerClk
Interrupts Interface
[IRQ0:6]GPIO17:23
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
[TrcClk]GPIO0
[TS1E]GPIO1
[TS2E]GPIO2
[TS1O]GPIO3
[TS2O]GPIO4
[TS3]GPIO5
[TS4]GPIO6
[TS5]GPIO7
[TS6]GPIO8
GPIO30
Halt
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I/O Specifications—266MHz
(Part 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3.
SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
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相關(guān)代理商/技術(shù)參數(shù) |
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