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參數(shù)資料
| 型號： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
8
SDRAM Memory Controller
The NPe405L Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to four logical banks. Up to
256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
Memory bus operates at same frequency as PLB
32-bit memory interface support
Programmable address compare for each bank of memory
- 4GB of address space
Industry standard 168-pin DIMMS are supported (some configurations)
Up to 133MHz Memory, includes PC133 support
4MB to 256MB per bank
Programmable address mapping and timing
Auto refresh
Page Mode Accesses with up to 4 open pages
Sync DRAM configuration via mode set command
Power Management (self-refresh)
Error Checking and Correction (ECC) support
- Standard SEC/DED coverage
- Aligned nibble error detect
- Address error logging
- Mixed ECC/non-ECC banks
- Bypass mode
External Peripheral Bus Controller (EBC)
Up to four ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported
Up to 66MHz operation
Burst and non-burst devices
8-, 16-bit byte-addressable data bus width support
Latch data on Ready, Synchronous or Asynchronous
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