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參數(shù)資料
| 型號(hào)： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 29/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
29
PHY0Col[PHY0Rx1Er]l
Collision [receive error] signal from the PHY. This is an
asynchronous signal (MII 0).
or
Receive Error ([RMII 1]).
I
5V tolerant
3.3V LVTTL
PHY0CrS[PHY0CrS0DV]
Carrier Sense signal from the PHY. This is an
asynchronous signal (MII 0).
or
Carrier sense data valid ([RMII 0]).
I
5V tolerant
3.3V LVTTL
1, 5
PHY0RxClk
Receiver medium clock. This signal is generated by the
PHY (MII 0).
I
5V tolerant
3.3V LVTTL
1, 4
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]
PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]
PHY0RxD2[PHY0Rx1D0]
PHY0RxD3[PHY0Rx1D1]
Received Data. This is a nibble wide bus from the PHY.
The data is synchronous with PHY0RxClk
(MII 0[RMII 0 and 1][SMII 0, 1, 2, and 3]).
I
5V tolerant
3.3V LVTTL
1, 4
PHY0RxDV[PHY0CrS1DV]
Receive Data Valid. Data on the Data Bus is valid when
this signal is activated. Deassertion of this signal indicates
end of the frame reception (MII 0).
or
Carrier sense data valid ([RMII 1])
I
5V tolerant
3.3V LVTTL
1, 5
PHY0RxErr[PHY0Rx0Er]
Receive Error. This signal comes from the PHY and is
synchronous with PHY0RxClk (MII 0 [RMII 0]).
I
5V tolerant
3.3V LVTTL
1, 5
PHY0TxClk[PHY0RefClk]
Transmit medium clock. This signal is generated the PHY
([MII 0]).
or
Reference Clock [RMII and SMII].
I
5V tolerant
3V LVTTL
1, 4
SDRAM Interface
MemData0:31
Memory Data bus
Notes:
1. MemData0 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
4
MemAddr12:0
Memory Address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr0 is the least significant bit (lsb).
O
3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lanes 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7.
I/O
3.3V LVTTL
4
Signal Functional Description
(Part 2 of 6)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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