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參數(shù)資料
| 型號(hào)： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 33/48頁 |
| 文件大小： | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
33
Trace Interface
[TS1E]
[TS2E]
Even Trace execution status.To access this function,
software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
[TS1O]
[TS2O]
Odd Trace execution status. To access this function,
software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
[TS3:6]
Trace Status. To access this function, software must toggle
a DCR bit.
O
5V tolerant
3.3V LVTTL
[TrcClk]
Trace interface clock. A toggling signal that is always half
of the CPU core frequency. To access this function,
software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
1, 6
Power Pins
GND
Ground
Note:
J09-J14, K09-K14, L09-L14, M09-M14, N09-N14,
and P09-P14 are also thermal balls.
I
Hardwire
V
DD
Logic voltage—2.5V
I
Hardwire
OV
DD
Output driver voltage—3.3V
I
Hardwire
AV
DD
Filtered PLL voltage—2.5V
I
3.3V DC
Wire w/ESD
Other Pins
Reserved
Do not connect signals, voltage, or ground to these pins.
n/a
n/a
Signal Functional Description
(Part 6 of 6)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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| POWERPAC-B | 制造商:IAR Systems 功能描述:PowerPac |
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