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參數(shù)資料
| 型號(hào)： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 5/48頁 |
| 文件大小： | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
5
NPe405L Embedded Controller Functional Block Diagram
The NPe405L is designed using the IBM Microelectronics Blue Logic
functional blocks are integrated to create an application-specific ASIC product. This approach provides a
consistent way to generate complex ASICs using IBM CoreConnect
TM
methodology in which major
TM
Bus Architecture.
Note:
IBM CoreConnect busses provide:
64-bit PLB interfaces up to 133MHz
32-bit OPB interfaces up to 66MHz
Address Map Support
The NPe405L incorporates two simple and separate address maps. The first is a fixed processor address
map that serves the PowerPC family of processors. This address map defines the possible contents of
various address regions which the processor can access. The second address map is for Device
Configuration Registers (DCR). This address map is accessed by software running on the NPe405L
processor through the use of
mtdcr
and
mfdcr
commands.
PPC405
Processor Core
DCU
ICU
DCR Bus
16KB
I-Cache
On-chip Peripheral Bus (OPB)
GPIO
IIC
UART
x2
DMA
Controller
(4-Channel)
Bridge
Processor Local Bus (PLB)
SDRAM
Controller
External
Bus
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
OPB
Interrupt
Controller
x2
Arb
- 28-bit addr
- 16-bit data
- 13-bit addr
- 32-bit data
Universal
8KB
D-Cache
DCRs
133 MHz max
66 MHz max
See Peripheral Interface
Clock Timing table
MAL8
Ethernet
x2
HDLCEX
32 channels
2 ports
ZMII
MII, RMII, SMII
MAL64
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