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參數(shù)資料
| 型號： | PowerNP NPe405L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
31
[DMAAck0:3]
Used by the NPe405L to indicate that data transfers have
occurred.
O
5V tolerant
3.3V LVTTL
[EOT0:3][TC0:3]
End Of Transfer[Terminal Count].
I/O
5V tolerant
3.3V LVTTL
1, 5
Internal Peripheral Interface
UARTSerClk
Serial Clock used to provide an alternative clock to the
internally generated serial clock. Used in cases where the
allowable internally generated baud rates are not
satisfactory. This input can be individually connected to
either or both UART0 and UART1.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Rx
UART0 Receive data.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Tx
UART0 Transmit data.
O
5V tolerant
3.3V LVTTL
[UART0_DCD]
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
1, 4
[UART0_DSR]
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
1, 4
[UART0_CTS]
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1, 4
[UART0_DTR]
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
[UART0_RTS]
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
[UART0_RI]
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL r
1, 4
UART1_Rx
UART1 Receive data.
I
5V tolerant
3.3V LVTTL
1, 4
UART1_Tx
UART1 Transmit data.
O
5V tolerant
3.3V LVTTL
[UART1_DCD]
UART1 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
1, 4
[UART1_DSR]
UART1 Data Set Ready.
I
5V tolerant
3.3V LVTTL
1, 4
[UART1_CTS]
UART1 Clear To Send.
I
5V tolerant
3.3V LVTTL
1, 4
[UART1_DTR]
UART1 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
6
[UART1_RTS]
UART1 Request To Send.
O
5V tolerant
3.3V LVTTL
6
[UART1_RI]
UART1 Ring Indicator.
I
5V tolerant
3.3V LVTTL
1, 4
Signal Functional Description
(Part 4 of 6)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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| PowerNP NPe405 | 32-Bit Embedded Processor(32位嵌入式處理器（應(yīng)用于網(wǎng)絡(luò)方面，提供高性價比）) |
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|---|---|
| POWERPAC-B | 制造商:IAR Systems 功能描述:PowerPac |
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