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參數(shù)資料
| 型號： | PowerNP NPe405H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 38/64頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | POWERNP NPE405H |
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Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
38
PCIGnt1:5
PCIGnt1:5 output when internal arbiter is used.
O
5V tolerant
3.3V PCI
HDLCEX Interface
HDLCEXTxClk
Transmit Clock
I
3.3V LVTTL
HDLCEXTxFS
Transmit Frame Synchronization
I
3.3V LVTTL
HDLCEXTxDataA
Transmit Data port A
O
3.3V LVTTL
HDLCEXTxDataB
Transmit Data port B
O
3.3V LVTTL
HDLCEXRxClk
Receive Clock
I
3.3V LVTTL
HDLCEXRxFS
Receive Frame Synchronization
I
3.3V LVTTL
HDLCEXRxDataA
Receive Data port A
I
3.3V LVTTL
HDLCEXRxDataB
Receive Data port B
I
3.3V LVTTL
[HDLCEXTxEnA]
Transmit Enable port A
O
5V tolerant
3.3V LVTTL
[HDLCEXTxEnB]
Transmit Enable port B
O
5V tolerant
3.3V LVTTL
HDLCMP Interface
HDLCMPTxClk0:3
Transmit Clock signal that controls the transmit bit rate
O
3.3V LVTTL
[HDLCMPTxClk4:7]
Transmit Clock signal that controls the transmit bit rate
O
5V tolerant
3.3V LVTTL
HDLCMPTxData0:3
Transmit Data signal
O
3.3V LVTTL
[HDLCMPTxData4:7]
Transmit Data signal
O
5V tolerant
3.3V LVTTL
[HDLCMPTxEn0:7]
Transmit Data Enable signal that controls when the
external buffer is tri-stated
O
5V tolerant
3.3V LVTTL
HDLCMPRxClk0:3
Receive Clock signal that controls the receive bit rate
I
3.3V LVTTL
[HDLCMPRxClk4:7]
Receive Clock signal that controls the receive bit rate
I
5V tolerant
3.3V LVTTL
HDLCMPRxData0:3
Receive Data signal
I
3.3V LVTTL
[HDLCMPRxData4:7]
Receive Data signal
I
5V tolerant
3.3V LVTTL
Ethernet Interface
EMC0MDClk
Management Data Clock. The MDClk is sourced to the
PHY. Management information is transferred
synchronously with respect to this clock (MII, RMII, and
SMII).
O
5V tolerant
3.3V LVTTL
EMC0MDIO
Management Data Input/Output is a bidirectional signal
between the Ethernet controller and the PHY. It is used to
transfer control and status information (MII, RMII, and
SMII).
I/O
5V tolerant
3.3V LVTTL
1, 4
Signal Functional Description
(Part 2 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
Signal Name
Description
I/O
Type
Notes
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