參數(shù)資料
型號(hào)： PowerNP NPe405H
廠商： IBM Microeletronics
英文描述： 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述： 32位嵌入式處理器（32位嵌入式處理器）
文件頁(yè)數(shù)： 10/64頁(yè)
文件大小： 1050K
代理商： POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
10
Programmable 2K clock time-out counter with disable for Ready
Programmable access timing per device
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Programmable address mapping
Peripheral Device pacing with external “Ready”
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
Four channels
Scatter/Gather capability for programming multiple DMA operations
8-, 16-, 32-bit peripheral support (OPB and external)
32-bit addressing
Address increment or decrement
Internal 32-byte data buffering capability
Supports internal and external peripherals
Support for memory mapped peripherals
Support for peripherals running on slower frequency buses
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