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參數(shù)資料
| 型號： | PowerNP NPe405H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 53/64頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | POWERNP NPE405H |
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Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
53
I/O Specifications—200MHz
(Part 1 of 5)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3.
SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
6.
PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns
for 33MHz.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
PCI Interface
PCIAD0:31
PCIC0:3[BE3:0]
PCIClk
PCIDevSel
PCIFrame
PCIGnt0[Req]
PCIGnt1:5
PCIIDSel
PCIINT[PerWE]
PCIIRDY
PCIParity
PCIPErr
PCIReq0[Gnt]
PCIReq1:5
PCIReset
PCISErr
PCIStop
12.3
12.3
n/a
12.3
12.3
15.5
15.5
n/a
15.5
15.5
PCIClk
PCIClk
6
6
n/a
n/a
async
6
6
PCIClk
PCIClk
n/a
n/a
12.3
15.5
PCIClk
6
n/a
12.3
12.3
12.3
12.3
n/a
15.5
15.5
15.5
15.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
6
n/a
n/a
async
6
6
6
n/a
n/a
n/a
n/a
PCIClk
6
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
12.3
12.3
12.3
15.5
15.5
15.5
PCIClk
PCIClk
PCIClk
6
6
PCITRDY
12.3
15.5
PCIClk
Ethernet Interface
EMC0MDClk
EMC0MDIO
EMC0TxD0:3
[EMC0Tx0:1D0:1
[EMC0Tx0:3D]
EMC0TxEn
[EMC0Tx0En]
[EMC0Sync]
EMC0TxErr
[EMC0Tx1En]
[EMC1TxD0:3]
[EMC1Tx2:3D0:1]
[EMC1TxEn]
[EMC1Tx2En]
[EMC1TxErr]
[EMC1Tx3En]
n/a
n/a
n/a
n/a
7.4
8.8
10.5
[7.3]
[5.0]
11.8
[7.2]
[5.6]
1.5
1.2
3.0
[2.3]
[1.7]
2.9
[2.3]
[1.7]
12
12
8
8
1, async
1
EMC0MDClk
n/a
n/a
12
8
PHYTX
1
n/a
n/a
12
8
PHYTX
1
n/a
n/a
11.8[7.4]
2.9[2.4]
12
8
PHYTX
1
12
8
12
8
12
8
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