參數(shù)資料
型號: PowerNP NPe405H
廠商: IBM Microeletronics
英文描述: 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述: 32位嵌入式處理器(32位嵌入式處理器)
文件頁數(shù): 11/64頁
文件大?。?/td> 1050K
代理商: POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
11
UART
Two 8-pin UART interfaces provided
Selectable internal or external serial clock to allow wide range of baud rates
Register compatibility with NS16550 register set
Complete status reporting capability
Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
Fully programmable serial-interface characteristics
Supports DMA using internal DMA engine
IIC Bus Interface
Compliant with Phillips Semiconductors I
2
C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed V
DD
IIC interface
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocol
Programmable error recovery
IIC EEPROM Controller
Supports setting of default initial conditions from serial EEPROM during system reset.
HDLCEX Interface
Multichannel HDLC controller core
Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 8 Mbps
32 transmit and 32 receive channels
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