參數(shù)資料
型號： PIC16F785
廠商： Microchip Technology Inc.
英文描述： 20-Pin Flash-Based 8-Bit CMOS Microcontroller with Two-Phase Asychronous Feedback PWM, Dual High-Speed Comparators and Dual Operational Amplifiers
中文描述： 20引腳基于閃存的8兩相異步反饋的PWM，雙高位CMOS微控制器的高速比較器和雙運算放大器
文件頁數(shù)： 89/178頁
文件大?。?/td> 1620K
代理商： PIC16F785
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 87
PIC16F785
13.0
TWO-PHASE PWM
The two-phase PWM (Pulse Width Modulator) is a
stand-alone peripheral that supports:
Single or dual-phase PWM
Single complementary output PWM with overlap/
delay
Sync input/output to cascade devices for addi-
tional phases
Setting either, or both, of the PH1EN or PH2EN bits of
the PWMCON0 register will activate the PWM module
(see Register 13-1). If PH1 is used then TRISC<1>
must be cleared to configure the pin as an output. The
same is true for TRISC<4> when using PH2.
13.1
PWM Period
The PWM period is derived from the main clock
(F
OSC
), the PWM prescaler and the period counter
(see Figure 13-3). The prescale bits (PWMP<1:0>,
see Register 13-2) determine the value of the clock
divider which divides the system clock (F
OSC
) to the
pwm_clk. This pwm_clk is used to drive the PWM
counter. In Master mode, the PWM counter is reset
when the count reaches the period count (PER<4:0>,
see Register 13-2), which determines the frequency of
the PWM. The relationship between the PWM
frequency, prescale and period count is shown in
Equation 13-1.
EQUATION 13-1:
PWM FREQUENCY
The maximum PWM frequency is F
OSC
/2, since the
period count must be greater than zero.
In Slave mode, the period counter is reset by the SYNC
input, which is the master device period counter reset.
For proper operation, the slave period count should be
equal to or greater than that of the master.
13.2
PWM Phase
Each enabled phase output is driven active when the
phase counter matches the corresponding PWM phase
count (PH<4:0>, see Register 13-4 and Register 13-5).
The phase output remains true until terminated by a
feedback signal from either of the comparators or the
auto shutdown activates.
Phase granularity is a function of the period count
value. For example, if PER<4:0> = 3, each output can
be shifted in 90
°
steps (see Equation 13-2)
.
EQUATION 13-2:
PHASE RESOLUTION
13.3
PWM Duty Cycle
Each PWM output is driven inactive, terminating the
drive period, by asynchronous feedback through the
internal comparators. The duty cycle resolution is in
effect infinitely adjustable. Either or both comparators
can be used to reset the PWM by setting the corre-
sponding comparator enable bit (CxEN, see
Register 13-3). Duty cycles of 100% can be obtained
by suppressing the feedback which would otherwise
terminate the pulse.
The comparator outputs can be “held off”, or blanked,
by enabling the corresponding BLANK bit (BLANKx,
see Register 13-1) for each phase. The blank bit
disables the comparator outputs for 1/2 of a system
clock (F
OSC
), thus ensuring at least Tosc/2 active time
for the PWM output. Blanking avoids early termination
of the PWM output which may result due to switching
transients at the beginning of the cycle.
13.4
Master/Slave Operation
Multiple chips can operate together to achieve addi-
tional phases by operating one as the master and the
others as slaves. When the PWM is configured as a
master, the RB7/SYNC pin is an output and generates
a high output for one pwm_clk period at the end of
each PWM period (see Figure 13-4).
When the PWM is configured as a slave, the RB7/
SYNC pin is an input. The high input from a master in
this configuration resets the PWM period counter
which synchronizes the slave unit at the end of each
PWM period. Proper operation of a slave device
requires a common external F
OSC
clock source to
drive the master and slave. The PWM prescale value
of the slave device must also be identical to that of the
master. As mentioned previously, the slave period
count value must be greater than or equal to that of
the master.
The PWM Counter will be reset and held at zero when
both PH1EN and PH2EN (PWMCON0<1:0>) are
false. If the PWM is configured as a slave, the PWM
Counter will remain reset at zero until the first SYNC
input is received.
PWM
FREQ
Fosc
(
2
PWMP
PER
1
+
)
(
)
---------------------------------------------------
=
Phase
DEG
360
PER
1
+
(
)
-------------------------
=
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參數(shù)描述
PIC16F785-E/ML 功能描述:8位微控制器 -MCU 3.5 KB 128 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-E/P 功能描述:8位微控制器 -MCU 14KB 368 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-E/SO 功能描述:8位微控制器 -MCU 3.5KB FL 128R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-E/SS 功能描述:8位微控制器 -MCU 3.5KB FL 128R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-I/ML 功能描述:8位微控制器 -MCU 3.5 KB 128 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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