參數(shù)資料
型號(hào)： PIC16F785
廠商： Microchip Technology Inc.
英文描述： 20-Pin Flash-Based 8-Bit CMOS Microcontroller with Two-Phase Asychronous Feedback PWM, Dual High-Speed Comparators and Dual Operational Amplifiers
中文描述： 20引腳基于閃存的8兩相異步反饋的PWM，雙高位CMOS微控制器的高速比較器和雙運(yùn)算放大器
文件頁(yè)數(shù)： 69/178頁(yè)
文件大?。?/td> 1620K
代理商： PIC16F785
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2004 Microchip Technology Inc.
Preliminary
DS41249A-page 67
PIC16F785
9.2
Comparator Outputs
The comparator outputs are read through the
CM1CON0, COM2CON0 or CM2CON1 registers.
CM1CON0 and CM2CON0 each contain the individ-
ual comparator output of comparator 1 and compara-
tor 2, respectively. CM2CON2 contains a mirror copy
of both comparator outputs facilitating a simultaneous
read of both comparators. These bits are read-only.
The comparator outputs may also be directly output to
the
RA2/AN2/T0CKI/INT/C1OUT
RC4/C2OUT/PH2 I/O pins. When enabled, multiplex-
ers in the output path of the RA2 and RC4 pins will
switch and the output of each pin will be the unsyn-
chronized output of the comparator. The uncertainty of
each of the comparators is related to the input offset
voltage and the response time given in the specifica-
tions. Figure 9-1 and Figure 9-2 show the output block
diagrams for Comparators 1 and 2, respectively.
and
The TRIS bits will still function as an output
enable/disable for the RA2/AN2/T0CKI/INT/C1OUT
and RC4/C2OUT/PH2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C1POL and C2POL bits (CMxCON0<4>).
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS
bit (CM2CON1<1>). The Timer1 gate feature can be
used to time the duration or interval of analog events.
The output of Comparator 2 can also be synchronized
with
Timer1
by
setting
(CM2CON1<0>). When enabled, the output of Com-
parator 2 is latched on the falling edge of Timer1 clock
source. If a prescaler is used with Timer1, Comparator
2 is latched after the prescaler. To prevent a race con-
dition, the Comparator 2 output is latched on the falling
edge of the Timer1 clock source and Timer1 incre-
ments on the rising edge of its clock source. See the
Comparator 2 Block Diagram (Figure 9-2) and the
Timer1 Block Diagram (Figure 6-1) for more informa-
tion.
the
C2SYNC
bit
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an increment.
9.3
Comparator Interrupts
The comparator interrupt flags are set whenever there
is a change in the output value of its respective compar-
ator. Software will need to maintain information about
the status of the output bits, as read from
CM2CON0<7:6>, to determine the actual change that
has occurred. The CxIF bits, PIR1<4:3>, are the
Comparator Interrupt Flags. Each comparator interrupt
bit must be reset in software by clearing it to ‘
0
’. Since
it is also possible to write a ‘
1
’ to this register, a simu-
lated interrupt may be initiated.
The CxIE bits (PIE1<4:3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupts. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CxIF bits will still be set if an interrupt condition occurs.
The comparator interrupt of the PIC16F785 differs from
previous designs in that the interrupt flag is set by the
mismatch edge and not the mismatch level. This
means that the interrupt flag can be reset without the
additional step of reading or writing the CMxCON0
register to clear the mismatch registers. When the
mismatch registers are not cleared, an interrupt will not
occur when the comparator output returns to the
previous state. When the mismatch registers are
cleared, an interrupt will occur when the comparator
returns to the previous state.
9.4
Effects of RESET
A RESET forces all registers to their RESET state. This
disables both comparators.
Note 1:
If a change in the CMxCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF (PIR1<4:3>)
interrupt flag may not get set.
2:
When either comparator is first enabled,
bias circuitry in the comparator module
may cause an invalid output from the
comparator until the bias circuitry is sta-
ble. Allow about 1
μ
s for bias settling then
clear the mismatch condition and inter-
rupt flags before enabling comparator
interrupts.
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參數(shù)描述
PIC16F785-E/ML 功能描述:8位微控制器 -MCU 3.5 KB 128 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F785-E/P 功能描述:8位微控制器 -MCU 14KB 368 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F785-E/SO 功能描述:8位微控制器 -MCU 3.5KB FL 128R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F785-E/SS 功能描述:8位微控制器 -MCU 3.5KB FL 128R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F785-I/ML 功能描述:8位微控制器 -MCU 3.5 KB 128 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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