參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 83/172頁
文件大?。?/td> 1506K
代理商： PIC16CR7X
2007 Microchip Technology Inc.
DS21993C-page 81
PIC16CR7X
TABLE 10-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
10.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master
mode, in that the shift clock is supplied externally at the
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
10.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP
instruction is executed, the following will occur:
a)
The first word will immediately transfer to the
TSR register and transmit when the master
device drives the CK line.
b)
The second word will remain in TXREG register.
c)
Flag bit TXIF will not be set.
d)
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e)
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
Follow these steps when setting up a Synchronous
Slave Transmission:
1.
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2.
Clear bits CREN and SREN.
3.
If interrupts are desired, then set enable bit
TXIE.
4.
If 9-bit transmission is desired, then set bit TX9.
5.
Enable the transmission by setting enable bit
TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the TXREG
register.
8.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
x
= unknown, – = unimplemented, read as ‘
0
’. Shaded cells are not used for synchronous master reception.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
PSPIF
(1)
SPEN
USART Receive Data Register
PSPIE
(1)
ADIE
CSRC
TX9
Baud Rate Generator Register
ADIF
RX9
RCIF
SREN
TXIF
CREN
SSPIF
—
CCP1IF
FERR
TMR2IF
OERR
TMR1IF
RX9D
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
RCIE
TXEN
TXIE
SYNC
SSPIE
—
CCP1IE
BRGH
TMR2IE
TRMT
TMR1IE
TX9D
1:
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