參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 47/172頁
文件大?。?/td> 1506K
代理商： PIC16CR7X
2007 Microchip Technology Inc.
DS21993C-page 45
PIC16CR7X
5.3
Prescaler
There is only one prescaler available on the microcon-
troller; it is shared exclusively between the Timer0 mod-
ule and the Watchdog Timer. The usage of the prescaler
is also mutually exclusive: that is, a prescaler assign-
ment for the Timer0 module means that there is no pres-
caler for the Watchdog Timer, and vice versa. This
prescaler is not readable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Examples of code for assigning the prescaler assign-
ment are shown in Example 5-1 and Example 5-2.
Note that when the prescaler is being assigned to the
WDT with ratios other than 1:1, lines 2 and 3 (high-
lighted) are optional. If a prescale ratio of 1:1 is used,
however, these lines must be used to set a temporary
value. The final 1:1 value is then set in lines 10 and 11
(highlighted). (Line numbers are included in the
example for illustrative purposes only, and are not part
of the actual code.)
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g.
CLRF
1,
MOVWF
1,
BSF
1,x
....etc.) will clear the prescaler. When assigned
to WDT, a
CLRWDT
instruction will clear the prescaler
along with the Watchdog Timer.
EXAMPLE 5-1:
1)
BSF
2)
MOVLW
3)
MOVWF
4)
BCF
5)
CLRF
6)
BSF
7)
MOVLW
8)
MOVWF
9)
CLRWDT
10) MOVLW
11) MOVWF
12) BCF
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
STATUS, RP0
; Bank1
b’xx0x0xxx’
; Select clock source and prescale value of
OPTION_REG
; other than 1:1
STATUS, RP0
; Bank0
TMR0
; Clear TMR0 and prescaler
STATUS, RP1
; Bank1
b’xxxx1xxx’
; Select WDT, do not change prescale value
OPTION_REG
; Clears WDT and prescaler
b’xxxx1xxx’
; Select new prescale value and WDT
OPTION_REG
STATUS, RP0
; Bank0
EXAMPLE 5-2:
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
01h,101h
TMR0
Timer0 Module Register
xxxx xxxx
uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
81h,181h
Legend:
OPTION_REG RBPU
x
= unknown,
u
= unchanged,
–
= unimplemented locations read as ‘
0
’. Shaded cells are not used by Timer0.
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
CLRWDT
BSF
MOVLW
MOVWF
BCF
; Clear WDT and prescaler
; Bank1
; Select TMR0, new prescale
; value and clock source
; Bank0
STATUS, RP0
b’xxxx0xxx’
OPTION_REG
STATUS, RP0
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