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| 型號(hào)： | PIC16CR7X |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 28/40-Pin, 8-Bit CMOS ROM Microcontrollers |
| 中文描述： | 28/40-Pin，8位微控制器的CMOS光盤 |
| 文件頁(yè)數(shù)： | 103/172頁(yè) |
| 文件大小： | 1506K |
| 代理商： | PIC16CR7X |
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2007 Microchip Technology Inc.
DS21993C-page 101
PIC16CR7X
12.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator, which does not require any external compo-
nents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKIN pin. That means that the
WDT will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a
SLEEP
instruction.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
Configuration bit, WDTE (
Section 12.1 “Configuration
Bits”
).
WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler), may be assigned
using the OPTION_REG register.
FIGURE 12-11:
WATCHDOG TIMER BLOCK DIAGRAM
TABLE 12-7:
SUMMARY OF WATCHDOG TIMER REGISTERS
Note 1:
The
CLRWDT
and
SLEEP
instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device Reset
condition.
2:
When a
CLRWDT
instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h,181h
Legend:
Note 1:
See Register 12-1 for operation of these bits.
Config. bits
OPTION_REG
Shaded cells are not used by the Watchdog Timer.
(1)
BOREN
(1)
INTEDG
—
CP0
T0SE
PWRTEN
(1)
PSA
WDTEN
PS2
FOSC1
PS1
FOSC0
PS0
RBPU
T0CS
From TMR0 Clock Source
(Figure 5-1)
To TMR0 (Figure 5-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8-to-1 MUX
PS2:PS0
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
8
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