參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 136/172頁
文件大?。?/td> 1506K
代理商： PIC16CR7X
PIC16CR7X
DS21993C-page 134
2007 Microchip Technology Inc.
TABLE 15-9:
I
2
C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100*
T
HIGH
Clock high time
100 kHz mode
4.0
—
μ
s
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
400 kHz mode
0.6
—
μ
s
SSP Module
100 kHz mode
1.5T
CY
4.7
—
—
101*
T
LOW
Clock low time
μ
s
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
400 kHz mode
1.3
—
μ
s
SSP Module
100 kHz mode
400 kHz mode
1.5T
CY
—
20 + 0.1C
B
—
102*
T
R
SDA and SCL rise
time
1000
300
ns
ns
C
B
is specified to be from
10-400 pF
103*
T
F
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1C
B
C
B
is specified to be from
10-400 pF
Only relevant for
Repeated Start
condition
After this period the first
clock pulse is generated
90*
T
SU
:
STA
Start condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
—
—
μ
s
μ
s
91*
T
HD
:
STA
Start condition hold
time
100 kHz mode
400 kHz mode
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
0.9
—
—
—
—
3500
—
—
—
μ
s
μ
s
ns
μ
s
ns
ns
μ
s
μ
s
ns
ns
μ
s
μ
s
106*
T
HD
:
DAT
Data input hold time 100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
107*
T
SU
:
DAT
Data input setup
time
(Note 2)
92*
T
SU
:
STO
Stop condition
setup time
109*
T
AA
Output valid from
clock
(Note 1)
110*
T
BUF
Bus free time
Time the bus must be free
before a new transmission
can start
C
B
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
2
C bus device can be used in a Standard mode (100 kHz) I
2
C bus system, but the
requirement T
SU
:
DAT
≥
250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line T
R
max. + T
SU
:
DAT
= 1000 + 250 = 1250 ns (according to the
Standard mode I
2
C bus specification), before the SCL line is released.
Bus capacitive loading
—
400
pF
*
Note 1:
2:
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