參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 18/172頁
文件大小： 1506K
代理商： PIC16CR7X
PIC16CR7X
DS21993C-page 16
2007 Microchip Technology Inc.
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Details
on page
Bank 0
00h
(4)
01h
02h
(4)
03h
(4)
04h
(4)
05h
06h
07h
08h
(5)
09h
(5)
0Ah
(1,4)
0Bh
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
TMR0
Timer0 Module Register
xxxx xxxx
45, 96
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
(2)
0001 1xxx
19, 96
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
27, 96
PORTA
PORTB
PORTC
—
—
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
--0x 0000
32, 96
34, 96
35, 96
xxxx xxxx
xxxx xxxx
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx
36, 96
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
39, 96
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
26, 96
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
0Ch
PIR1
PSPIF
(3)
—
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
23, 96
0Dh
0Eh
0Fh
PIR2
TMR1L
TMR1H
—
—
—
—
—
—
CCP2IF
---- ---0
24, 96
50, 96
50, 96
xxxx xxxx
xxxx xxxx
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
47, 96
52, 96
52, 96
Timer2 Module Register
—
TOUTPS3
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
—
—
CCP1X
SPEN
RX9
SREN
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
—
—
CCP2X
A/D Result Register Byte
0000 0000
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON T2CKPS1 T2CKPS0
-000 0000
xxxx xxxx
64, 68, 96
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
61, 96
56, 96
56, 96
54, 96
70, 96
75, 96
77, 96
58, 96
58, 96
54, 96
88, 96
xxxx xxxx
xxxx xxxx
CCP1Y
CREN
CCP1M3
—
CCP1M2
FERR
CCP1M1
OERR
CCP1M0
RX9D
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
xxxx xxxx
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/
DONE
—
ADON
0000 00-0
83, 96
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, – = unimplemented, read as ‘
0
’, r = reserved.
Shaded locations are unimplemented, read as ‘
0
’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (
CALL
or
GOTO
).
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘
0
’.
This bit always reads as a ‘
1
’.
Note
1:
2:
3:
4:
5:
6:
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