參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 57/172頁
文件大?。?/td> 1506K
代理商： PIC16CR7X
2007 Microchip Technology Inc.
DS21993C-page 55
PIC16CR7X
8.3
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the
following and is configured by CCPxCON<3:0>:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value is overwritten by the new
captured value.
8.3.1
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
CCP PIN CONFIGURATION
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
8.3.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.3.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
8.3.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 8-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
;Turn CCP module off
NEW_CAPT_PS;Load the W reg with
;the new prescaler
;move value and CCP ON
CCP1CON
;Load CCP1CON with this
;value
8.4
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Driven high
Driven low
Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Note:
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set Flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RC2/CCP1
pin
Prescaler
÷
1, 4, 16
and
Edge Detect
CLRF
MOVLW
CCP1CON
MOVWF
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
Q
S
R
Output
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
RC2/CCP1
Pin
TRISC<2>
Output Enable
CCP1CON<3:0>
Mode Select
Special Event Trigger will:
clear TMR1H and TMR1L registers
NOT set interrupt flag bit TMR1F (PIR1<0>)
(for CCP2 only) set the GO/DONE bit (ADCON0<2>)
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