參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 25/172頁
文件大?。?/td> 1506K
代理商： PIC16CR7X
2007 Microchip Technology Inc.
DS21993C-page 23
PIC16CR7X
2.2.2.5
PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
PIR1: (ADDRESS 0Ch)
R/W-0
PSPIF
(1)
bit 7
R/W-0
ADIF
R-0
RCIF
R-0
TXIF
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIF
(1)
:
Parallel Slave Port Read/Write Interrupt Flag bit
1
= A read or a write operation has taken place (must be cleared in software)
0
= No read or write has occurred
ADIF
: A/D Converter Interrupt Flag bit
1
= An A/D conversion is completed (must be cleared in software)
0
= The A/D conversion is not complete
RCIF
: USART Receive Interrupt Flag bit
1
= The USART receive buffer is full
0
= The USART receive buffer is empty
TXIF
: USART Transmit Interrupt Flag bit
1
= The USART transmit buffer is empty
0
= The USART transmit buffer is full
SSPIF
: Synchronous Serial Port (SSP) Interrupt Flag
1
= The SSP interrupt condition has occurred, and must be cleared in software before
returning from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I
2
C Slave
A transmission/reception has taken place.
I
2
C Master
A transmission/reception has taken place.
The initiated Start condition was completed by the SSP module.
The initiated Stop condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A Start condition occurred while the SSP module was Idle (multi-master system).
A Stop condition occurred while the SSP module was Idle (multi-master system).
0
= No SSP interrupt condition has occurred
CCP1IF
: CCP1 Interrupt Flag bit
Capture mode:
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare mode:
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TMR2IF
: TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match occurred (must be cleared in software)
0
= No TMR2 to PR2 match occurred
TMR1IF
: TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
PSPIF is reserved on 28-pin devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note
1:
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