參數(shù)資料
型號(hào)： pentium processor
廠商： Intel Corp.
英文描述： 32 Bit Processor With MMX And Mobile Module(32位帶移動(dòng)模塊和MMX技術(shù)CPU)
中文描述： 32位處理器MMX和移動(dòng)模塊（32位帶移動(dòng)模塊和MMX公司技術(shù)的CPU）
文件頁(yè)數(shù)： 9/35頁(yè)
文件大小： 550K
代理商： PENTIUM PROCESSOR
E
INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
9
9/19/97 1:03 PM SPEIDEN_.DOC
Table 3. PCI Signal Descriptions
Name
Type
Voltage
Description
specifications.
2.1.3.
SIDEBAND (9 SIGNALS)
PROCESSOR/PIIX4 ISA BRIDGE
Table 4 lists the
Intel Mobile Module’s processor
and PIIX4 ISA bridge sideband signals at the
connector interface. (Refer to the PIIX4 ISA Bridge
External Architecture (Order Number 290562-001)
Table 4. Processor/PIIX4 ISA Bridge Sideband Signal Descriptions
for complete signal descriptions and detailed
functions.) The voltage level for these signals is
determined by V_CPUIO, which is supplied by the
Intel Mobile Module. These signals are open-drain
and should have a pullup resistor on the
I/O Module.
Name
Type
Voltage
Description
FERR#
O
V_CPUIO
Numeric Coprocessor Error:
This pin functions as a FERR#
signal supporting coprocessor errors. This signal is tied to the
coprocessor error signal on the processor and is driven by the
processor to the PIIX4 ISA bridge.
Note: this signal does NOT
require a pull up on the I/O module. A pull-up is present on the
processor module.
*CPURST
I
V_CPUIO
Processor Reset:
The PIIX4 ISA bridge asserts CPURST to reset
the processor. The PIIX4 ISA bridge asserts CPURST# during
power-up and when a hard reset sequence is initiated through the
RC register.
*IGNNE#
I
V_CPUIO
Ignore Error:
This signal is connected to the ignore error pin on the
processor and is driven by the PIIX4 ISA bridge.
*INIT#
I
V_CPUIO
Initialization:
INIT is asserted by the PIIX4 ISA bridge to the
processor for system initialization.
NOTE:
The system manufacturer should provide a pull up/pull down option on this pin,
and connect this PIIX4 ISA bridge input to the Intel Mobile Module connector
PIN BB38.
Processor Interrupt:
INTR is driven by the PIIX4 ISA bridge to
signal the processor that an interrupt request is pending and needs
to be serviced.
*INTR
I
V_CPUIO
*NMI
I
V_CPUIO
Non-Maskable Interrupt:
NMI is used to force a non-maskable
interrupt to the processor.
The PIIX4 ISA bridge generates an NMI
when either SERR# or IOCHK# is asserted, depending on how the
NMI Status and Control Register is programmed.
*A20M#
I
V_CPUIO
Address Bit 20 Mask:
When enabled, this causes the processor to
emulate the address wraparound at one Mbyte which occurs on the
Intel 8086 processor.
*SMI#
I
V_CPUIO
System Management Interrupt:
SMI# is an active low
synchronous output that is asserted by the PIIX4 ISA bridge in
response to one of many enabled hardware or software events.
The
SMI# signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
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