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參數(shù)資料
| 型號(hào)： | pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Processor With MMX And Mobile Module(32位帶移動(dòng)模塊和MMX技術(shù)CPU) |
| 中文描述： | 32位處理器MMX和移動(dòng)模塊（32位帶移動(dòng)模塊和MMX公司技術(shù)的CPU） |
| 文件頁數(shù)： | 23/35頁 |
| 文件大?。?/td> | 550K |
| 代理商： | PENTIUM PROCESSOR |
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E
For proper signal routing, the System OEM must
determine the memory configuration that will be
supported during the 430TX PCIset generation of
mobile modules. If the I/O planar is designed to
support four banks of memory and 64-Mbit
SDRAM memory devices, then the System OEM
should route the upper two address signals from
the
Intel Mobile Module’s address pins MA[12:13]
to the upper order address bits on the SODIMM
socket and not the RAS[4:5]# pins. Subsequently if
the I/O design supports six banks of memory and
does not intend to support 64-Mbit memory
devices, then RAS[4:5]# should be routed from the
Intel Mobile Module’s RAS[4:5]# pins to the
SODIMM RAS pins.
INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
23
9/19/97 1:03 PM SPEIDEN_.DOC
Even though these two sets of Intel Mobile Module
pins are electrically equivalent on the module,
connecting the memory address and control
signals
as
suggested
compatibility with future modules.
will
help
maintain
NOTE
The 430TX PCIset does not support six
banks of memory and 64-Mbit SDRAM
devices simultaneously, however, future
PCIsets may provide this flexibility. To
design today for this type of upgrade, it is
recommended that Q-switches be used on
either the RAS[4:5]# or MA[12:13] signals,
or both. This would ensure that the trace
lengths of the RAS signals are kept to a
minimum, and
signal
compromised.
quality
is
not
3.3.3.
PCI INTERFACE
The 430TX PCIset is compliant with the PCI 2.1
specification, which improves the worst-case PCI
bus access latency from earlier PCI specifications.
The complete PCI interface of the 430TX PCIset is
available at the Intel Mobile Module’s connector.
The 430TX PCIset supports the PCI Clockrun
protocol for power management of PCI. In this
protocol, PCI devices assert the CLKRUN# open-
drain signal when they require the use of the PCI
interface. (Refer to the PCI Mobile addendum for
complete details on the PCI Clockrun protocol.)
The 430TX PCIset is responsible for arbitrating the
PCI bus. When configured in Mobile Mode, the
430TX PCIset can support up to four PCI bus
masters. There are four PCI Request/Grant pairs,
REQ[3:0]# and GNT[3:0]# available on the
connector to the system manufacturer I/O Module.
The 430TX PCIset supports only Mechanism #1
for accessing PCI configuration space, as detailed
in the PCI specification. This implies that signals
AD[31:11] are available for PCI IDSEL signals.
However, since the 430TX PCIset is always device
#0; AD11 will never be asserted during PCI
configuration cycles as an IDSEL. Thus, AD12 is
the first available address line usable as an IDSEL.
3.4.
Regulation
Processor Core Voltage
The Intel Mobile Module supports an input DC
voltage range of 5V - 20V (+5 percent) slew-rate
controlled from the system battery/power supply.
Maximum peak input voltage is 21.1V including
ripple.
The Intel Mobile Module’s DC voltage regulator
(DC/DC converter) is designed to support the CPU
core voltage and the 2.5V-only CPU interface
signals so no special voltage regulation is required
on the system electronics. The CPU interface
signals between the CPU and PIIX4 South Bridge
require proper termination to the V_CPUIO (2.5V)
power plane and should be treated with special
attention. Please refer the pin definition for
recommended resistor termination values.
3.4.1.
EFFICIENCY
VOLTAGE REGULATOR
The voltage regulator is optimized for Pentium
Processors and is most efficient in the 1A to 3A
range. When placed in suspend mode, the module
will consume approximately 20mW. See Table 12
for details over the entire current range.
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