參數(shù)資料
型號(hào)： pentium processor
廠商： Intel Corp.
英文描述： 32 Bit Processor With MMX And Mobile Module(32位帶移動(dòng)模塊和MMX技術(shù)CPU)
中文描述： 32位處理器MMX和移動(dòng)模塊（32位帶移動(dòng)模塊和MMX公司技術(shù)的CPU）
文件頁(yè)數(shù)： 20/35頁(yè)
文件大?。?/td> 550K
代理商： PENTIUM PROCESSOR
INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
E
Table 11. Connector Specifications
20
9/19/97 1:03 PM SPEIDEN_.DOC
Parameter
Condition
Specification
Mechanical
Mating Cycles
50 cycles
Connector Mating Force
0.9N (90gf) max. Per contact
Contact Un-mating Force
0.1N (10gf) min. Per contact
3.0.
FUNCTIONAL DESCPRIPTION
3.1.
Intel Mobile Module
The Intel Mobile Module will support the mobile
Pentium Processor with MMX technology running
at 200/66, and 233/66 MHz with 16 KB on-chip code
and data cache sizes.
3.2.
The mobile Pentium Processor with MMX
technology internal cache is complimented with a
second-level 2.5V cache using a high-performance
pipeline burst SRAM. The L2 cache can support up
to 64 MB of system memory, the maximum amount of
cacheable system memory supported by the 430TX
PCIset system controller. The Intel Mobile Module
has two 100-pin TSOP (Thin Small Outline Package)
footprints for 512K direct-mapped write-back L2
cache.
L2 Cache
The Intel Mobile Module supports the ZZ, or snooze
mode power management features in current pipeline
burst SRAM (PBSRAM). The PIIX4 ISA bridge
Southbridge component on the I/O Module is the
source for the generation of ZZ mode. This ZZ signal
is named L2_ZZ on the Intel Mobile Module interface,
clarifying its sole purpose of ZZ support for second-
level cache.
3.3.
Controller
430TX PCIset System
Intel’s 430TX PCIset system controller is a highly
integrated device that combines the mobile Pentium
Processor bus controller, the DRAM controller,
second-level cache controller and PCI bus
CLKRUN# is a feature that enables controlling of
the PCI clock on or off
430TX PCIset suspend modes include Suspend
to RAM (STR), Suspend to Disk (STD) and
Powered On Suspend (POS)
System Management RAM (SMRAM) power
management modes include Compatible SMRAM
(C_SMRAM)
and
(E_SMRAM). C_SMRAM is the traditional
SMRAM feature implemented in all Intel PCI
chipsets. E_SMRAM is a new feature that
supports write-back cacheable SMRAM space
up to 1Mbyte. To minimize power consumption
while the system is idle, the internal 430TX
PCIset clock is turned off (gated off) when there
is no processor and PCI activity.
Extended
SMRAM
The Intel Mobile Module supports only the 430TX
PCIset features available in the Mobile Mode of
operation. Refer to Intel’s latest revision of the 430TX
PCIset specification for complete details.
3.3.1.
MEMORY ORGANIZATION
The complete memory interface of the 430TX PCIset
is available at the Intel Mobile Module’s connector; all
of the 430TX PCIset Mobile Mode memory
configurations
and
modes
supported. Two memory features not supported by
the 430TX PCIset Mobile Mode are Parity and Error
Detection and Correction (EDC).
of
operation
are
DRAM technologies supported by 430TX PCIset
include Extended Data Out (EDO) and SDRAM.
NOTE
The Intel Mobile Module does not support the
use of fast page mode (FPM) memory on the
I/O Module.
These memory types may be mixed in the system,
but only on a row-by-row basis. In other words, all
DRAM in a particular row (RAS[5:0]#) must be of the
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