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參數(shù)資料
| 型號： | pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Processor With MMX And Mobile Module(32位帶移動模塊和MMX技術(shù)CPU) |
| 中文描述： | 32位處理器MMX和移動模塊（32位帶移動模塊和MMX公司技術(shù)的CPU） |
| 文件頁數(shù)： | 26/35頁 |
| 文件大?。?/td> | 550K |
| 代理商： | PENTIUM PROCESSOR |
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INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
E
Voltage Plane Sequencing
26
9/19/97 1:03 PM SPEIDEN_.DOC
V_DC
VR_PWRGD
V_CORE
V_3S
VR_ON
V_CPUIO
V_5S
RSMRST#
10 MS MIN
6 MS MAX
1 MS MIN
1. PWROK on I/O board should be active on when VR_PWRGD is active and V_3S is good.
2. CPU_RST from I/O board should be active for a minimum of 6 ms after PWROK is active and PLL_STP# and CPU_STP# are
inactive. Note that PLL_STP# is an AND condition of RSMRST# and SUSB# on the PIIX4.
V_3
V_5
0 MS MIN
0 MS MIN
0 MS MIN
Figure 4. Power On Sequence Timing
Figure 4 details the sequencing of Signals and
Voltage planes required for normal operation of the
Intel Mobile Module.
The Intel Mobile Module also provides the
VR_PWRGD signal, which indicates that the
voltage regulator power is operating at a stable
voltage level. The system manufacturer should use
this signal on the I/O Module to control power
inputs, and gate PWROK to the PIIX4 South
Bridge.
See the Intel Mobile Module Design Guide(Order
Number 243339) for more details about the voltage
regulator, power sequencing, and proper voltage
signaling.
3.5.
Active Thermal Feedback
Table 14 identifies three addresses allocated for
the System Management Bus (SMBus) on the
Intel Mobile Module. Two of these addresses are
reserved for future use.
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